 Three forces seem to be converging to make life miserable for system-level IC developers. The first comes masquerading as a friend: End-system requirements increasingly demand system-level integration for their electronic content, securing the job prospects for system-on-chip (SoC) designers. But as integration rises, the cost and risk of a design spin are spiraling. Unfortunately, spins aren't all-or even mostly, according to some data-caused by design error. Often they are the result of misinterpretations of, errors in or simply changes to the design requirements. This makes developing an SoC for any but a well-understood application enough of a risk to give pause to everyone involved. The third force is exacerbating the second: the fragmentation and transience of end markets. This phenomenon, which seems to be limiting the size of any one end-user market to about 50 units over a total product life of 27 minutes, has generally been blamed on consumer electronics. But it is probably a good deal more pervasive than that. Even industrial and instrumentation markets are seeing shorter product cycles and a proliferation of end products. Put these three forces together, and you have a problem: the need to modify the functionality of complex SoCs both during and after the initial design cycle, but without incurring huge incremental design or bill-of-materials costs. The obvious solution, of course, is to implement the SoC in an FPGA. For most applications that is not feasible. The next alternative, to embed a programmable fabric of some sort, whether field- or mask-programmable, is gaining interest as designs move from 130 to 90 nanometers. But the technology is still beyond the reach of most design teams. That leaves only a couple of options. One is to put any functionality subject to doubt in software or on highly configurable hardware (or a combination). This has its costs in terms of power and die area, and no systems architect likes the thought of even more functionality migrating to software, where it is guaranteed to be implemented incorrectly. But it's an alternative most of the time. The other possibility is to embed the volatile functionality in an external component that can be changed more easily that the big SoC. This part is most commonly, these days, one of the very inexpensive new moderate-size FPGAs on the market. But if power, speed or cost are major issues, it can also be an important role for a structured ASIC. That is the basis of a new marketing program from structured ASIC vendor ChipX. Elie Massabki, vice president of marketing there, is seeing this approach gain favor, particularly in the set-top-box and printer markets, where function volatility is high and cost pressure severe. Massabki pointed out that even if the parts cost for a particular version of the system went up slightly, the overall cost of ownership-including design investment, parts cost across the whole product line, with amortized NRE and including risk factors-could be significantly less. The approach may require a good deal more thought during the system-partitioning process, and it has the potential to blow up in the architects' faces if a careful watch isn't kept on pin counts and bit rates as the functional blocks are partitioned between the two chips. But, particularly with the growing maturity of multidice packaging, there is gold in them thar hills. Ron Wilson covers microprocessors, programmable/reconfigurable logic and chip design. Contact him at rwilson@cmp.com. | 
