May. 28, 2013 - S2C announced today a new family of its fifth-generation product, the K7 TAI Logic Module, based on Xilinx’s 28-nm Kintex-7 FPGA devices. The K7 TAI Logic Module provides up to 4.1 million ASIC gates of capacity, 432 external I/O and 16 channels of Gigabit Transceivers capable of running up to 10Gbps. ...

May. 21, 2013 - EnSilica has announced that it has partnered with Cross Border Technologies to accelerate the sales of both its IC design services and system IP solutions in key European and Asian markets, particularly Germany, France, Japan and Korea.

May. 14, 2013 - Jasper Design Automation has announced the availability of its new JasperGold® Low Power Verification App (JG-LPV App) which enables users to utilize formal methods for the verification of SOC designs optimized for lower power consumption with multiple voltage and power-management domains.

May. 07, 2013 - S3 Group today announced that it has licensed a custom ADC and DAC solution to Avalent Technologies for the development of their latest SoC.

May. 01, 2013 - CircuitSutra Technologies announced the release of their SystemC model library consisting of CircuitSutra Modeling Library (CSTML) and the Virtual Platform – Quick Start Package (VP-QSP), which can be used in the Virtual Platform project.

Apr. 09, 2013 - Tensilica, Inc. today announced that Inomize, the largest Israeli ASIC solutions firm, is now a qualified Tensilica design center. Inomize will work with Tensilica’s growing Israeli customer base to manage complex chip design projects.

Apr. 08, 2013 - Mentor Graphics today announced availability of the first, comprehensive IP to System, UPF-based low-power verification flow. The IEEE-1801 UPF (Unified Power Format) has emerged as the low- power standard that enables designers to specify a design’s power intent separately from the design itself ...

Mar. 21, 2013 - ARM and Synopsys today announced the availability of optimized 28-nanometer (nm) Synopsys Reference Implementations for ARM Cortex-A15 MPCore and Cortex-A7 MPCore processor clusters as well as the CoreLink CCI-400 cache-coherent interconnect.

Mar. 11, 2013 - Toshiba America Electronic Components today announces availability of a new Metal-Configurable Standard Cell (MCSC) platform SoC. The platform SoC employs an innovative MCSC architecture that speeds ASIC development for faster time-to-market at lower non-recurring engineering (NRE) costs

Feb. 28, 2013 - In perhaps a first for any Indian company so far, Dreamchip Electronics Private Limited, a fabless semiconductor company founded in 2012 has announced plans for launching SoCs for tablet computers. The SoCs come in 3 different variants named Siddhi, Vani and Sandesh. Each of these has been specified ...

Feb. 18, 2013 - S3 Group today announced the immediate availability of a number of new Mixed-Signal IP cores which have been developed and silicon proven during 2012.

Feb. 06, 2013 - Cadence announced today that two of its major foundry partners—Samsung Foundry and GLOBALFOUNDRIES—are supporting new Cadence® custom/analog technology targeting designs at the advanced nodes of 20 and 14 nanometers.

Feb. 04, 2013 - TU Dresden today announced the successful initial operation of a low-power test-chip featuring a Tensilica Xtensa LX4 DSP equipped with RacyICs power management IP implemented in GLOBALFOUNDRIES’ advanced 28nm Super Low Power (SLP) technology

Jan. 31, 2013 - Cadence today announced production-proven verification IP (VIP) for the new USB SuperSpeed Inter-Chip (SSIC) specification, enabling customers to thoroughly verify designs deploying the latest extension of the USB 3.0 protocol.

Jan. 28, 2013 - S2C announced today the addition of 13 new Prototype Ready interface cards and accessories to its growing library of pre-engineered hardware and software components aimed at accelerating the development of SoC prototypes.

Jan. 22, 2013 - Cadence today introduced a new version of its leading functional verification platform and methodologies, featuring a broad set of new and enhanced capabilities which double the productivity of SoC verification over the previous release.

Jan. 21, 2013 - S2C Inc. today announced the addition of the newest prototyping platform, Quad V7, to its V7 TAI Logic Module series, a new generation of SoC/ASIC prototyping hardware based on Xilinx’s Virtex®-7 2000T All Programmable 3D ICs.

Nov. 27, 2012 - Cadence today announced the immediate availability of the industry’s first Automotive Ethernet Design IP and Verification IP (VIP) for the latest Automotive Ethernet Controllers. The standards-based Design IP and VIP support the latest Automotive Ethernet extensions as defined by the OPEN Alliance ...

Oct. 29, 2012 - CEVA today announced that Inomize, the largest Israeli ASIC solutions firm, has joined the CEVAnet Partner Program, officially becoming an Approved Design Center for CEVA's customers.

Oct. 18, 2012 - Mentor Graphics today announced new formal-based technologies in the Questa® Verification Platform that provide mainstream users with the ability to more easily perform exhaustive formal verification analysis.

Oct. 09, 2012 - TSMC announced today that the readiness of 20nm and CoWoS™ design support within the Open Innovation Platform® (OIP) is demonstrated by the delivery of two foundry-first reference flows supporting 20nm and CoWoS™ (Chip on Wafer on Subsrate) technologies.

Oct. 01, 2012 - Memoir Systems today announced the availability of the second offering of its revolutionary commercial products: Renaissance™4X. Renaissance 4X increases the memory performance of existing embedded memory macros by delivering up to a 4X increase in memory operations per second (MOPS).

Sep. 05, 2012 - Synopsys today announced the 100th design win of its DesignWare IP optimized for 28-nm. The silicon-proven 28-nm portfolio consists of widely-used IP including PHYs for USB, PCI Express, SATA, HDMI, DDR, MIPI, as well as data converters, audio codecs, embedded memories and logic libraries, with tens ...

Aug. 28, 2012 - ARM and Synopsys have signed a multi-year agreement that expands Synopsys' access to a broad range of ARM IP. The two companies will broaden their collaboration to enable SoC designers to optimize the power and performance of ARM technology-based SoCs with Synopsys Galaxy Implementation Platform and ...

Aug. 22, 2012 - Sonics today announced that Intel has licensed key IP components from Sonics portfolio of system IP for use in its SoC platforms -- which incorporate the Intel® Atom™ processor. Intel will work with Sonics to rapidly, intelligently and securely integrate a wide array of third party IP onto its SoC ...

Aug. 10, 2012 - Novocell Semiconductor has responded to the demands of their growing number of military, aerospace, and automotive industry customers, announcing today that their Smartbit™-based antifuse OTP memory designs have completed the rigorous exposure to long term high temperature exposure required for Military ...

Aug. 08, 2012 - Synopsys today announced the launch of VIP-Central.org, the first industry-wide, technical community site focused on system-on-chip (SoC) verification engineers and users of verification IP (VIP).

Jul. 26, 2012 - Vivado Design Suite 2012.2 delivers a highly Integrated Design Environment (IDE) with a completely new generation of system-to-IC tools that include High-Level Synthesis, RTL Synthesis with the industry's best SystemVerilog support, revolutionary analytical place and route, and an advanced SDC-based ...

Jul. 11, 2012 - Cadence today announced powerful new capabilities in its PCI Express® Verification IP (PCIe® VIP) which result in more in-depth verification of the most current PCI Express specification at both the block and system-on-chip (SoC) levels.

Jul. 02, 2012 - S2C announces that TAKUMI, a Japan-based advanced Graphics IP provider, has implemented a series of Graphics IP cores on S2C’s rapid FPGA-based prototyping systems including GS3000 and GSV3000 cores.

Jun. 26, 2012 - Synopsys and SMIC today announced availability of version 5.0 of their 40-nanometer (nm) RTL-to-GDSII reference design flow.

Jun. 01, 2012 - GLOBALFOUNDRIES plans to demonstrate an enhanced silicon-validated design flow for its 28nm Super Low Power (SLP) technology with Gate First High-k Metal Gate (HKMG). In addition, the company will reveal jointly developed design flows with its EDA partners in certifying both analog and digital "double ...

Jun. 01, 2012 - S2C today announced that it has added ARM1176 and ARM926 GUC test chip modules to the comprehensive family of Prototype Ready™ accessories used to create FPGA-based prototypes and to interface FPGA-based prototype boards to the user’s target operating environment.

May. 31, 2012 - Cadence today announced that it has contributed to STMicroelectronics having taped out a 20-nanometer test chip, incorporating custom analog and digital methodologies to enable mixed-signal SoC design at this advanced process node.

May. 22, 2012 - NanGate today announced the release of its V5 Library Creator Platform for advanced process node SoC design, including support for 20/22nm process technology.

May. 15, 2012 - Access to the latest Vivante IP cores, give HiSilicon an innovative technology platform based on the latest 3D, CGPU (Composition GPU) and GPGPU APIs. The latest agreement enables HiSilicon to deliver the highest graphics performance in products spanning its entire portfolio.

May. 15, 2012 - ICScape Inc. today announced that after enabling over 100 successful customer tapeouts, it is now ready to market its solutions worldwide. The expansion is driven by US$28 million in financial backing the company received in 2011, mostly from China Electronics Corporation (CEC), China’s largest electronics ...

May. 14, 2012 - Sigrity today introduced XcitePI IO Interconnect Model Extraction as part of the company’s comprehensive suite of high-speed analysis software products. This breakthrough technology generates precise chip IO power/ground and signal interconnect models for accurate system-level analysis of high-speed ...

Apr. 30, 2012 - Cadence today announced TripleCheck IP Validator, a new addition to the Cadence Verification IP (VIP) Catalog that simplifies and accelerates compliance testing of interface design IP. The expanding Cadence VIP Catalog is helping leading system and semiconductor companies quickly and thoroughly verify ...

Apr. 18, 2012 - Soitec announced today its fully depleted (FD) product roadmap comprising two products designed for both planar and three-dimensional (FinFET) approaches to building transistors.