Oct. 20, 2009 - Synopsys today announced that it has created an optimized reference implementation methodology for the ARM® Cortex™-A8 processor that achieves greater than 2GHz (4000 DMIPS) at 540mW.

Oct. 19, 2009 - Cadence and ARM today announced that the two companies have entered into a strategic collaboration to create a next-generation SoC design flow that will accelerate time to market and lower the cost of SoC integration and verification.

Oct. 19, 2009 - Cadence today announced that SMIC has adopted Cadence(R) Litho Physical Analyzer and Cadence Litho Electrical Analyzer to more accurately predict the impact of stress and lithographic variability on the performance of 65- and 45-nanometer semiconductor designs

Oct. 12, 2009 - Synopsys today introduced its Synphony HLS (High Level Synthesis) solution that integrates M-language and model-based synthesis to deliver up to 10X higher design and verification productivity than traditional RTL flows for communications and multimedia applications.

Oct. 08, 2009 - The Open Virtual Platforms (OVP) initiative has released new models of ARM processor cores. These models work with the OVP simulator, OVPsim, and have exceptionally fast performance of hundreds of millions of instructions per second (MIPS).

Oct. 06, 2009 - The Cadence® Incisive® Enterprise Simulator (IES) and Incisive Software Extensions (ISX) TLM verification solutions now support Open Verification Methodology (OVM)-based TLM hardware/software co-verification, unified TLM and C/C++ hardware/software co-debugging, plus embedded software symbolic debug ...

Oct. 05, 2009 - New Integrated Solution Increases Return on Investment from Assertion-Based Verification and Eases Adoption for Design and Verification Engineers

Oct. 01, 2009 - Cadence today announced it has developed Open Verification Methodology (OVM)-based verification IP (VIP) to assist developers working with the emerging PCI Express Base Specification 3.0 (PCIe 3.0) interconnect protocol, which is currently under development within the PCI-SIG at a preliminary revision ...

Oct. 01, 2009 - Silicon & Software today announced that it has joined the Power Forward Initiative (PFI). Established by Cadence Design Systems, Inc. and its partners to develop comprehensive approaches to power-efficient design, PFI now welcomes S3 as the organization continues to advance low power standards and solutions. ...

Sep. 21, 2009 - Under the terms of the agreement Global Unichip will support customers by translating their designs into netlists for the metal-programmable portion of the CAP™. Netlists will be mapped onto a CAP emulation board for validation before being transferred to Atmel for place & route and metal programming. ...

Sep. 16, 2009 - Denali today announced Denali's PureSpec(TM) verification IP support for IBM's PowerPC(R) processor local bus (PLB)-6, enabling verification of compliance with the latest PLB specification and validation of interoperability between the processor cores and integrated bus controllers.

Sep. 15, 2009 - IPextreme today announced the immediate availability of Freescale’s 32-bit V1 ColdFire, National Semiconductor’s 16-bit CR16 and Freescale’s 8-bit HCS08 synthesizable microprocessor IP cores to Toppan’s design service customers.

Sep. 14, 2009 - Atollic TrueSTUDIO® development environment options reduce cost and speed implementation of embedded systems based on Toshiba ARM926EJ-S™ and ARM Cortex™-M3 families

Sep. 14, 2009 - Synopsys today announced that TSMC has adopted Synopsys' HSIM® hierarchical FastSPICE circuit simulator for its sub-40-nanometer (nm) memory intellectual property (IP) characterization flow.

Sep. 08, 2009 - Xilinx today announced demonstrations of the latest developments in serial connectivity that lower the cost and power of serial digital interfaces and enable the rapid adoption of emerging DisplayPort and Ethernet AVB protocols.

Aug. 31, 2009 - GSA announce the appointment of Warren Savage, president and chief executive officer of IPextreme, to serve as the GSA IP Interest Group Chairman.

Aug. 31, 2009 - As part of the agreement, GLOBALFOUNDRIES has adopted a comprehensive suite of Cadence® technologies to aid in the design, verification and manufacturing of complex semiconductor devices targeting process technologies of 45 nanometers and below. In addition, GLOBALFOUNDRIES will team with the Cadence ...

Aug. 27, 2009 -

Aug. 06, 2009 - Global Unichip announced its Gbps level high speed production-proven total solution. The total solution includes comprehensive IP portfolio, ASIC implementation, chip + package co-design, and production testing solution.

Aug. 03, 2009 - Actel continues to lead the way for low-power designs with the release of Libero® Integrated Design Environment (IDE) v8.6. The newest version of the Libero IDE offers designers several new features, including upgraded power analysis using the SmartPower tool and post-layout probe insertion for device ...

Jul. 29, 2009 - Cadence reported second quarter 2009 revenue of $210 million, compared to revenue of $308 million reported for the same period in 2008. On a GAAP basis, Cadence recognized a net loss of $74 million, or $(0.29) per share on a diluted basis, in the second quarter of 2009, compared to a net loss of $19 ...

Jul. 28, 2009 - SystemVerilog (SV) along with its methodologies is emerging as a unified language for design and verification using object oriented techniques. Companies who have already invested in Specman ‘e’ test benches face a dilemma whether to continue supporting legacy verification infrastructure for future ...

Jul. 27, 2009 - Global Unichip announced today the application and validation of System-in-Package (SiP) design solution in TSMC Reference Flow 10.0 as the fruit of collaboration with TSMC. The SiP methodology has been fully qualified with GUC production case and achieved good silicon correlation.

Jul. 24, 2009 - Denali Software today announced the availability of the extended PureSpec™ verification IP solution with planning and protocol exploration capabilities, plus seamless integration into 3rd party verification planners, such as Synopsys® VMM Planner.

Jul. 22, 2009 - Mentor and Cadence today announced that the Accellera guide for verification IP (VIP) interoperability, currently in draft form, was enabled by technology contributions provided by both companies in open source form, and served as a basis for the reference implementation of the Accellera VIP Technical ...

Jul. 16, 2009 - The Cadence® solution combines C-to-Silicon Compiler with new memory compiler integration and C/C++ usability, Incisive® Enterprise Simulator with new TLM/RTL metric-driven verification and source level debug visualization, Calypto® sequential logic equivalence checking, the first version of the ...

Jul. 15, 2009 - Synopsys today announced its complete DesignWare® IP solution for PCI Express® (PCIe®) 3.0 consisting of digital controllers, PHY and verification IP. Synopsys' DesignWare IP enables easy integration of the 8.0 GT/s PCI Express 3.0 interface into system-on-chips (SoCs) for high-performance enterprise ...

Jul. 10, 2009 - Avery Design Systems today announced that its PCI-Xactor verification IP solution now supports the PCI Express® (PCIe®) 3.0 draft standard, at a preliminary revision 0.5, and is available to existing customers under active maintenance.

Jul. 09, 2009 - InSilica Inc. announced that it has taken a license to use BA22 RISC Processor solution from Beyond Semiconductor in its next generation camera processors. The value to InSilica of Beyond Semiconductor's IP solution is to reduce power in its camera processor SoCs while reducing overall silicon area ...

Jul. 07, 2009 - Atrenta today announced a collaboration with Sonics and Denali to build a reference flow based on Atrenta’s 1Team®-Genesis automated chip assembly product. The flow will facilitate a healthy eco-system of semiconductor IP that is qualified and ready to use in automated SoC assembly.

Jul. 07, 2009 - MIPS and EE Solutions announced they are teaming to provide semiconductor companies in China and Taiwan with easy access to MIPS' industry-standard technology. EE Solutions licensed the synthesizable MIPS32(R) 24KEc(TM) core as part of its digital IP portfolio and will work with MIPS to provide value-added ...

Jul. 01, 2009 - ST-Ericsson selected MVSIM for its proven ability to comprehensively verify low power techniques, including standby and built-in automated low power assertions, which enable the early detection of bugs. The tool's extensive support for the IEEE 1801 [Unified Power Format (UPF)] power format, on which ...

Jun. 24, 2009 - IEEE-Standard Encryption for SecureIP Models Offers 2X Performance Boost; Open Verification Methodology (OVM) to Increase Schedule Predictability and Quality

Jun. 24, 2009 - Xilinx today released the Xilinx Base Targeted Design Platform aimed at accelerating the development of system-on-chip (SoC) solutions with Xilinx(R) Virtex(R)-6 and Spartan(R)-6 field programmable gate arrays (FPGAs).

Jun. 19, 2009 - Tiempo will reveal at the 46th DAC, its unique and breakthrough asynchronous synthesis tool. ACC (“Asynchronous Circuit Compiler”) is the first synthesis tool on the market which automatically generates asynchronous and delay-insensitive circuits from a model written in a standard hardware description ...

Jun. 16, 2009 - eASIC and IPextreme today announced the immediate availability of Freescale’s 32-bit V1 and V2 ColdFire processor cores for Nextreme NEW ASICs.

Jun. 16, 2009 - Innovative Logic announced today the second release of USB 3.0 Device Controller IP. Inno-Logic’s USB3.0 IP offering includes implementation IP as well as verification IP by making use of industry standard latest tools and methodologies.

Jun. 11, 2009 - Sonics, Inc., and IPextreme Inc., announce today that Sonics has joined the IPextreme Constellations program, which is designed to make semiconductor IP more accessible to a greater number of SoC designers.

Jun. 11, 2009 - Upon completion, Cadence expects to achieve annual operating expense savings of approximately $30 million, through a combination of workforce and other expense reductions.

Jun. 08, 2009 - Cadence today announced that Casio Computer Co., Ltd., has selected the Cadence® C-to-Silicon Compiler as its high-level synthesis solution.