Sep. 16, 2009 - Denali today announced Denali's PureSpec(TM) verification IP support for IBM's PowerPC(R) processor local bus (PLB)-6, enabling verification of compliance with the latest PLB specification and validation of interoperability between the processor cores and integrated bus controllers.

Sep. 15, 2009 - IPextreme today announced the immediate availability of Freescale’s 32-bit V1 ColdFire, National Semiconductor’s 16-bit CR16 and Freescale’s 8-bit HCS08 synthesizable microprocessor IP cores to Toppan’s design service customers.

Sep. 14, 2009 - Atollic TrueSTUDIO® development environment options reduce cost and speed implementation of embedded systems based on Toshiba ARM926EJ-S™ and ARM Cortex™-M3 families

Sep. 14, 2009 - Synopsys today announced that TSMC has adopted Synopsys' HSIM® hierarchical FastSPICE circuit simulator for its sub-40-nanometer (nm) memory intellectual property (IP) characterization flow.

Sep. 08, 2009 - Xilinx today announced demonstrations of the latest developments in serial connectivity that lower the cost and power of serial digital interfaces and enable the rapid adoption of emerging DisplayPort and Ethernet AVB protocols.

Aug. 31, 2009 - GSA announce the appointment of Warren Savage, president and chief executive officer of IPextreme, to serve as the GSA IP Interest Group Chairman.

Aug. 31, 2009 - As part of the agreement, GLOBALFOUNDRIES has adopted a comprehensive suite of Cadence® technologies to aid in the design, verification and manufacturing of complex semiconductor devices targeting process technologies of 45 nanometers and below. In addition, GLOBALFOUNDRIES will team with the Cadence ...

Aug. 27, 2009 -

Aug. 06, 2009 - Global Unichip announced its Gbps level high speed production-proven total solution. The total solution includes comprehensive IP portfolio, ASIC implementation, chip + package co-design, and production testing solution.

Aug. 03, 2009 - Actel continues to lead the way for low-power designs with the release of Libero® Integrated Design Environment (IDE) v8.6. The newest version of the Libero IDE offers designers several new features, including upgraded power analysis using the SmartPower tool and post-layout probe insertion for device ...

Jul. 29, 2009 - Cadence reported second quarter 2009 revenue of $210 million, compared to revenue of $308 million reported for the same period in 2008. On a GAAP basis, Cadence recognized a net loss of $74 million, or $(0.29) per share on a diluted basis, in the second quarter of 2009, compared to a net loss of $19 ...

Jul. 28, 2009 - SystemVerilog (SV) along with its methodologies is emerging as a unified language for design and verification using object oriented techniques. Companies who have already invested in Specman ‘e’ test benches face a dilemma whether to continue supporting legacy verification infrastructure for future ...

Jul. 27, 2009 - Global Unichip announced today the application and validation of System-in-Package (SiP) design solution in TSMC Reference Flow 10.0 as the fruit of collaboration with TSMC. The SiP methodology has been fully qualified with GUC production case and achieved good silicon correlation.

Jul. 24, 2009 - Denali Software today announced the availability of the extended PureSpec™ verification IP solution with planning and protocol exploration capabilities, plus seamless integration into 3rd party verification planners, such as Synopsys® VMM Planner.

Jul. 22, 2009 - Mentor and Cadence today announced that the Accellera guide for verification IP (VIP) interoperability, currently in draft form, was enabled by technology contributions provided by both companies in open source form, and served as a basis for the reference implementation of the Accellera VIP Technical ...

Jul. 16, 2009 - The Cadence® solution combines C-to-Silicon Compiler with new memory compiler integration and C/C++ usability, Incisive® Enterprise Simulator with new TLM/RTL metric-driven verification and source level debug visualization, Calypto® sequential logic equivalence checking, the first version of the ...

Jul. 15, 2009 - Synopsys today announced its complete DesignWare® IP solution for PCI Express® (PCIe®) 3.0 consisting of digital controllers, PHY and verification IP. Synopsys' DesignWare IP enables easy integration of the 8.0 GT/s PCI Express 3.0 interface into system-on-chips (SoCs) for high-performance enterprise ...

Jul. 10, 2009 - Avery Design Systems today announced that its PCI-Xactor verification IP solution now supports the PCI Express® (PCIe®) 3.0 draft standard, at a preliminary revision 0.5, and is available to existing customers under active maintenance.

Jul. 09, 2009 - InSilica Inc. announced that it has taken a license to use BA22 RISC Processor solution from Beyond Semiconductor in its next generation camera processors. The value to InSilica of Beyond Semiconductor's IP solution is to reduce power in its camera processor SoCs while reducing overall silicon area ...

Jul. 07, 2009 - Atrenta today announced a collaboration with Sonics and Denali to build a reference flow based on Atrenta’s 1Team®-Genesis automated chip assembly product. The flow will facilitate a healthy eco-system of semiconductor IP that is qualified and ready to use in automated SoC assembly.

Jul. 07, 2009 - MIPS and EE Solutions announced they are teaming to provide semiconductor companies in China and Taiwan with easy access to MIPS' industry-standard technology. EE Solutions licensed the synthesizable MIPS32(R) 24KEc(TM) core as part of its digital IP portfolio and will work with MIPS to provide value-added ...

Jul. 01, 2009 - ST-Ericsson selected MVSIM for its proven ability to comprehensively verify low power techniques, including standby and built-in automated low power assertions, which enable the early detection of bugs. The tool's extensive support for the IEEE 1801 [Unified Power Format (UPF)] power format, on which ...

Jun. 24, 2009 - IEEE-Standard Encryption for SecureIP Models Offers 2X Performance Boost; Open Verification Methodology (OVM) to Increase Schedule Predictability and Quality

Jun. 24, 2009 - Xilinx today released the Xilinx Base Targeted Design Platform aimed at accelerating the development of system-on-chip (SoC) solutions with Xilinx(R) Virtex(R)-6 and Spartan(R)-6 field programmable gate arrays (FPGAs).

Jun. 19, 2009 - Tiempo will reveal at the 46th DAC, its unique and breakthrough asynchronous synthesis tool. ACC (“Asynchronous Circuit Compiler”) is the first synthesis tool on the market which automatically generates asynchronous and delay-insensitive circuits from a model written in a standard hardware description ...

Jun. 16, 2009 - eASIC and IPextreme today announced the immediate availability of Freescale’s 32-bit V1 and V2 ColdFire processor cores for Nextreme NEW ASICs.

Jun. 16, 2009 - Innovative Logic announced today the second release of USB 3.0 Device Controller IP. Inno-Logic’s USB3.0 IP offering includes implementation IP as well as verification IP by making use of industry standard latest tools and methodologies.

Jun. 11, 2009 - Sonics, Inc., and IPextreme Inc., announce today that Sonics has joined the IPextreme Constellations program, which is designed to make semiconductor IP more accessible to a greater number of SoC designers.

Jun. 11, 2009 - Upon completion, Cadence expects to achieve annual operating expense savings of approximately $30 million, through a combination of workforce and other expense reductions.

Jun. 08, 2009 - Cadence today announced that Casio Computer Co., Ltd., has selected the Cadence® C-to-Silicon Compiler as its high-level synthesis solution.

Jun. 08, 2009 - Open to electronic design automation (EDA) vendors, intellectual property (IP) vendors, embedded software companies and service providers, the program is designed to benefit mutual customers by advancing tool and model interoperability as well as availability of system-level models and services.

May. 19, 2009 - Jasper Design Automation, provider of advanced formal technology solutions, today announced its JasperGold® Verification System has been adopted by ARM.

May. 19, 2009 - Cadence and Virtutech today announced a collaboration to integrate Cadence® Incisive® Software Extensions with the Virtutech Simics® high-speed system-level virtual platform.

May. 19, 2009 - Cadence announced today that it has delivered an extended system-level verification solution that supports the Open SystemC Initiative (OSCI) TLM 2.0 standard.

May. 18, 2009 - Cadence Design Systems announced today that NXP Semiconductors utilized the new Cadence® Encounter® Digital Implementation System (EDI System), and its seamless design-for-manufacturing (DFM) technologies to ensure reliable production of its advanced 45-nanometer PNX85500 digital TV processor chip ...

May. 18, 2009 - Cadence today announced that PLDA utilized Cadence® Incisive® USB 3.0 (SuperSpeed USB) verification IP (VIP) to achieve IP success for its commercial USB 3.0 design IP.

May. 12, 2009 - Octasic today announced that Robert Blake has been appointed chief executive officer. Blake, who until recently served as vice president of consumer and automotive business at Altera Corporation, brings more than 20 years of industry experience to Octasic.

May. 07, 2009 - Cadence announced today that Gennum Corporation’s Snowbush IP Group utilized the Cadence® Encounter® Digital Implementation System to develop the industry’s first 45-nanometer SuperSpeed USB 3.0 PHY IP core.

Apr. 30, 2009 - Cadence reported first quarter 2009 revenue of $206 million, compared to revenue of $271 million reported for the same period in 2008. On a GAAP basis, Cadence recognized a net loss of $63 million, or $(0.25) per share on a diluted basis, in the first quarter of 2009, compared to a net loss of $33 million, ...

Apr. 28, 2009 - Synopsys today announced that Tego, Inc. has standardized on the production-proven VMM verification methodology and VCS® functional verification solution, both key components of Synopsys' Discovery™ Verification Platform, to verify their radio frequency identification (RFID) tags for the aviation ...