NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
1611 Results (801 - 840) |
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Cadence Introduces Industry's First Family of MIPI Standard-Compliant OVM Multi-Language Verification IP
Dec. 04, 2008 - Cadence Design Systems today introduced six additional verification IP (VIP) to its Incisive® VIP portfolio, each designed to speed verification of designs based on the emerging Mobile Industry Processor Interface (MIPISM) standard. -
EVE Forms EVE University Connection Program
Dec. 02, 2008 - EVE today announced the formation of the EVE University Connection Program created to supply universities with first-rate technology to bridge the integration of hardware and software for system-on-chip (SoC) design. -
CHiL Semiconductor Selects Virage Logic's Flexible AEON(R) Non-Volatile Embedded Memory
Dec. 02, 2008 - CHiL Semiconductor delivers highly intelligent and flexible power management solutions to the server CPU and memory, desktop CPU and graphics GPU markets, where enhanced performance, digital communication and energy efficiency are key metrics. The use of NVM in CHiL's solutions is transforming these ... -
Cadence Announces Appointments of R&D and Worldwide Field Operations Leaders
Nov. 21, 2008 - Cadence Design Systems today announced the promotion of three senior leaders to executive management positions in R&D and Worldwide Sales and Field Operations. All three positions report to the Interim Office of the Chief Executive. -
Teridian Semiconductor Licenses ColdFire Architecture from IPextreme
Nov. 20, 2008 - IPextreme today announced that Teridian Semiconductor Corp., a leading supplier of mixed-signal integrated circuits (ICs) used in energy, automation, networking, and secure access systems, has licensed Freescale’s V2 ColdFire® SPP IP core through IPextreme. -
Cadence Announces Development of OVM Verification IP for USB 3.0 and PCI Express 3.0 High-Speed Protocols
Nov. 17, 2008 - Cadence Design Systems today announced the planned first quarter 2009 availability of new Open Verification Methodology (OVM) verification IP (VIP) for two key high-speed protocols: USB 3.0 and PCI Express 3.0. -
Atrenta Announces "SpyGlass(R) Clean" Flow with Leading ESL Synthesis Providers
Nov. 10, 2008 - SpyLinks(TM) Program Initiative Enables High Quality Register Transfer Level (RTL) Output from Electronic System Level (ESL) Synthesis Tools -
ARM Announces Industry's First Silicon-on-Insulator Physical IP Library for IBM's New 45nm SOI Foundry
Nov. 10, 2008 - ARM today announced the industry's first Silicon-on-Insulator (SOI) physical IP library including standard cell, memory and I/O libraries for IBM's fully enabled 45nm SOI foundry, also announced today. -
Cadence Announces Restructuring Program
Nov. 06, 2008 - The company expects to eliminate at least 625 full-time positions, representing 12% of its global employee base, plus a substantial number of contractors and consultants. -
Wipro-NewLogic and IN2FAB Technology launch Analog and Mixed Signal "Port on Demand" service
Nov. 04, 2008 - The co-operation enables IC designs and IP to be ported to a manufacturing standard in just a few weeks, typically offering upto 10X reductions in cycle time and engineering costs as well as freeing up customer’s engineers to focus on other potentially higher value added activities. -
Cadence Expands Portfolio of System-Level Verification IP and SpeedBridge Adapters to Boost Acceleration and Emulation Performance
Nov. 04, 2008 - The New System VIP and SpeedBridge Adapters Speed Up Time to Market and Improve Quality, Further Extending Cadence Leadership in VIP Portfolio Breadth and Depth -
Silicon Interfaces announces the release of its Verification Methodology Manual (VMM) based USB 2.0 SystemVerilog Verification IP
Nov. 03, 2008 - The USB2.0 VIP is developed using SystemVerilog test benches based on VMM methodology using coverage-driven, constrained-random and assertion-based techniques. -
Cadence Announces Accounting Review and Postpones Release of Third Quarter 2008 Financial Results and Webcast
Oct. 23, 2008 - Cadence initiated the review after preliminarily determining during its regular review of its third quarter results that approximately $24 million of revenue relating to these contracts was recognized during the first quarter of 2008, but should have been recognized ratably over the duration of the ... -
KPIT Cummins and VaST Partner to Deliver Virtualization Tools and Services to Improve Software Quality for Automotive OEMs & ODMs
Oct. 20, 2008 - The partnership between VaST and KPIT Cummins focuses on methodology adoption services that speed the deployment of advanced virtual prototyping tools and methodologies such as networked ECU Virtual-Hardware-In-the-Loop simulations. -
Silicon Interfaces announces the release of its Open Verification Methodology (OVM) Based Gigabit Ethernet MAC SystemVerilog OVC
Oct. 16, 2008 - Silicon Interfaces’ GEMAC core implements the Ethernet Media Access Control (MAC) protocol according to IEEE 802.3 specification. The MAC has a standard Gigabit Media Independent Interface (GMII) to connect to any PHY interface. -
Cadence Expands Enterprise Verification IP Portfolio by 5X to Provide Industry's Broadest OVM Multi-Language Offering
Oct. 15, 2008 - VIP Portfolio Extends to Over 30 Industry-Standard Protocols, Enabling Customers to Improve Schedule Predictability, Productivity, and Product Quality -
Cadence Board of Directors Creates Interim Office of the Chief Executive; Michael Fister Resigns
Oct. 15, 2008 - The formation of the Interim Office of the Chief Executive followed Michael Fister’s resignation as President, Chief Executive Officer and a director of the company, by mutual agreement between Mr. Fister and the Board. -
Cadence Collaborates With ARM to Deliver Hardware/Software Emulation Environment, Accelerating Processor-Based Design
Oct. 07, 2008 - Cadence Design Systems announced today the availability of an ARM hardware/software co-verification environment that accelerates the system validation process and provides mutual customers with a faster path to first silicon working with early software. -
Silicon Interfaces announces its OVM Based IEEE 1394 Link Layer Controller Verification IP
Oct. 06, 2008 - Silicon Interfaces announces the availability of their OVM Based IEEE 1394-1995/1394a-2000 Link Layer Controller Open Verification Component (OVC) supporting multi-language verification environments. -
IPextreme and Texas Instruments Host Webinar on "cJTAG – IEEE 1149.7: Next Generation Test and Debug"
Oct. 03, 2008 - IPextreme and Texas Instruments will hold a webinar on Thursday, October 9, 2008 on the first semiconductor IP solution to implement the new IEEE 1149.7 test and debug standard. -
OKI Network LSI Reduces Test Time 90% by Combining the Open Verification Methodology (OVM) and Cadence Incisive Technologies
Sep. 24, 2008 - OKI Network LSI Co., Ltd., is reporting significant benefits from its use of the Open Verification Methodology (OVM) with Cadence Incisive functional verification technology. Co-developed by Cadence and released last year, the OVM is the first scalable, open, multi-vendor verification methodology for ... -
Domino Logic in ASIC Design Flow - Detailed Methodology and Breakthroughs in High Speed Design Automation Approach
Sep. 22, 2008 - Engineers at STMicroelectronic have revealed how to use domino logic, a very fast circuit design style utilized in the highest performance custom designs,in an automated framework. -
IPextreme Provides Solarflare Additional Licenses of Infineon C166SV1 Microcontroller IP
Sep. 18, 2008 - IPextreme and Solarflare announced that after a successful release of the 10Xpress SFT9001 10GBASE-T PHY, the existing C166SV1 Microcontroller license has been extended. -
Achronix Semiconductor Launched to Break through FPGA Performance Barriers
Sep. 16, 2008 - Achronix Semiconductor today announced that it has already begun shipping the world's fastest FPGAs. The Speedster family, with the SPD60 as its initial member, delivers speeds up to 1.5 GHz, which represents a three-fold increase in performance over existing FPGAs. -
Nuvation Introduces the Multichannel Video Front End Reference Design for Design-Acceleration of Video Security Encoder Products
Sep. 15, 2008 - Nuvation's McVFE reference design is based on Texas Instruments' (TI) DaVinci(TM) technology and TVP quad-channel video decoder with complementary FPGA technology provided by Xilinx's Spartan 3A FPGA technology. -
New Release of the OVM Takes Verification to the Next Level
Sep. 11, 2008 - The new release extends the proven sequential stimulus mechanism in the OVM with transaction-level modeling (TLM) interfaces to improve the modularity and reuse of stimulus sequences. Other enhancements include direct support for parameterized classes in the OVM factory and built-in debug support for ... -
Sequence, Faraday, NemoChips Team To Slash Over 50% Of Total Power From Advanced Mobile Processor Design
Sep. 11, 2008 - Pairing Sequence Design's PowerTheater, and the low-power design expertise of NemoChips and Faraday Technology Corporation, led to a 52 percent reduction in total power for an advanced mobile processor design. -
Cadence Introduces SaaS Solutions for Semiconductor Design
Sep. 10, 2008 - These production-proven, ready-to-go design environments are accessible via the Internet and provide design teams a faster time-to-productivity with reduced risk and cost. Cadence Hosted Design Solutions are available for custom IC design, logic design, physical design, advanced low power, functional ... -
Cadence Expands Enterprise Verification Solution to Include Planning, Unified Verification Metrics and Industry Databases
Sep. 09, 2008 - With these enhancements, project managers can now more easily create verification plans, expand the scope and scalability of project metrics being managed, and uniquely combine formal verification, testbench simulation, and verification acceleration metrics for integrated verification process management. ... -
Cadence Extends Low-Power Leadership With Early Dynamic Power Analysis and Pre-RTL Exploration
Sep. 08, 2008 - In Breakthrough for System-Level Design, Cadence Reveals Technologies to Enable Early Exploration of Chip and System Power Requirements -
Certess Certitude Increases Verification Quality at Mellanox Technologies
Sep. 04, 2008 - Certitude is the first commercial functional qualification software product for companies developing systems on a chip (SoCs) or integrating intellectual property (IP) blocks. Certitude certifies that if a semiconductor chip design had a bug, it would be found. -
Cosmic Circuits Experiences 8X Performance Gains by Adopting Cadence Virtuoso Spectre with Turbo Technology
Aug. 25, 2008 - Cosmic Circuits was looking for a SPICE simulator that would deliver a significant boost in speed without compromising on accuracy. The Spectre simulator, with its recently introduced turbo technology, enabled Cosmic Circuits to improve simulation runtime for design verification—accelerating time ... -
Mentor Graphics and Altera Partner on DO-254
Aug. 19, 2008 - Mentor Joins Altera’s DO-254 Global Partner Network; Announces Joint Development of DO-254-Certifiable IP -
Imperas Announces Verification, Licensing, Distribution Agreement With MIPS Technologies
Aug. 19, 2008 - Imperas models of MIPS® processor cores will be verified by MIPS Technologies under the MIPS-Verified™ program. -
Cadence Withdraws Proposal to Acquire Mentor Graphics
Aug. 15, 2008 - Cadence Design Systems today announced that it has withdrawn its proposal to acquire all of the outstanding shares of Mentor Graphics common stock -
BitSim joins Mentor Graphics's Questa Vanguard Program (QVP)
Aug. 07, 2008 - BitSim as a QVP partners provides support for advanced verification methods, conversion services, training and consulting based on Mentor Graphics industry leading Questa verification platform. -
Actel Offers Additional Power Reduction and Simplifies Design Creation With Libero IDE 8.4
Aug. 04, 2008 - Enables Design Reuse; Extends FPGA Core Operating Voltage Range; and Allows Users to Compare and Contrast Multiple Power Scenarios -
Open Verification Methodology Helps KPIT Cummins Boost Productivity, Shorten Turnaround Time
Jul. 31, 2008 - The OVM, which Cadence Helped Develop, Enabled KPIT Cummins to Quickly Find Bugs in Its IP Design -
OKI Turns to Cadence and the Open Verification Methodology (OVM) to Speed Product Development
Jul. 29, 2008 - OVM Enables OKI to Improve Verification IP Integration and Compress Testbench Development by 30% -
Cadence Reports Q2 Revenue of $329 Million
Jul. 24, 2008 - Cadence Design Systems, Inc. today reported second quarter 2008 revenue of $329 million, compared to revenue of $391 million reported for the same period in 2007.