Sep. 17, 2007 - The Hz4120 and Hz3120 integrate real time dual HD AVC, VC-1, DV/HDV or MPEG2/4 decoder & AVC, VC1, MPEG2/4 encoder/transcoder, along with an advanced audio processor, embedded application CPU, 2D/3D graphics accelerator and multi-plane display processor into a single chip, thus enabling end-users to ...

Sep. 17, 2007 - The library provides high- performance SystemC transaction-level simulation models (TLMs) for assembling virtual platforms, including instruction set simulators (ISS), and TLMs of Synopsys' DesignWare Cores and ARM® AMBA® interconnect components. All DesignWare System-Level Library models are written ...

Sep. 10, 2007 - This low-power reference design methodology (LP-RDM) together with the Cadence® Low Power Solution ensures that ARC’s new Energy PRO technology is captured in RTL and implemented consistently throughout the design flow to GDSII. Users of the reference design flow may achieve up to a four-fold reduction ...

Sep. 04, 2007 - The two companies have collaborated and now offer highly adaptable PCI Express digital cores and PHY IP from Rambus, tightly integrated and verified with Cadence verification IP.

Aug. 27, 2007 - The kit provides complete example verification plans, transaction-level and cycle-accurate models, design and verification IP, scripts and libraries -- all proven on a wireless segment representative design and delivered through applicability consulting.

Aug. 23, 2007 - The Accellera OVL standard includes a library of assertion checkers provided as an open standard. It improves electronic design verification when using Hardware Description Languages (HDLs) and results in better quality designs by enabling effective use of ABV methodologies.

Aug. 23, 2007 - Kilopass XPM technology is the world’s first high-density embedded NVM technology verified in silicon and available for design in 65 nm standard logic CMOS processes. Kilopass is also making XPM-65LP and XPM-65G+ evaluation kits available to its customers.

Aug. 22, 2007 - Sonics announced today that Sonics SMART Interconnect solutions are now available as library elements for Mentor Graphics' Vista(TM) and Visual Elite(TM) products. Mentor Graphics now offers a complete configuration, analysis and verification of SystemC SoC platforms based on Sonics SMART Interconnect ...

Aug. 21, 2007 - With the release of version 9.2 of the AccelDSP(TM) synthesis tool and System Generator for DSP, the development tool component of the Xilinx(R) XtremeDSP(TM) solution, provides higher-levels of performance as well as a tighter integration between the two tools to simplify the FPGA design flow for developers ...

Aug. 17, 2007 - Combined with Cadence's existing DFM methodologies and capabilities, the acquisition uniquely positions Cadence® as the only EDA company that can deliver manufacturing awareness and lithographic correctness for all layers in an IC from transistor through interconnect, in designs ranging from SoCs to ...

Aug. 16, 2007 - The Open Verification Methodology (OVM) will deliver a tool-independent solution for designers and verification engineers that promotes data portability and interoperability. It delivers on the promise of SystemVerilog with established interoperability mechanisms for Verification IP (VIP), transaction-level ...

Aug. 14, 2007 - Xilinx engineers will be joined by Cadence Design Systems, Inc., Mentor Graphics Corporation, and Synopsys, Inc. to define and implement new verification flows to maximize productivity and quality of results for ultra high-density designs targeting today's 65nm FPGAs as well as new and emerging FPGA ...

Aug. 13, 2007 - ARC International today announced that its new Video Subsystems have garnered very favorable reviews by a broad range of leaders throughout the semiconductor industry. They include ARC partners such as Cadence Design Systems, CoWare, Green Hills Software, Magma Design Automation, and Virage Logic. Industry ...

Aug. 07, 2007 - The planned acquisition will expand Virage Logic's ability to serve the company's chosen market by adding new products and services required in the rapid development of System-on-Chip (SoC) integrated circuits to Virage Logic's current family of memory compilers, logic libraries and related development ...

Aug. 03, 2007 - Abraxas Corporation, a leading risk mitigation technology company headquartered in McLean, Virginia announces the purchase of Intrinsix Federal Systems, a division of Intrinsix Corp. of Westboro, Massachusetts. Intrinsix Federal Systems (IFS) is based in Maryland and supports defense electronics.

Aug. 02, 2007 - Certess, Inc. today announced that Juniper Networks, the leader in high-performance networking, has adopted Certitude, the first commercial functional qualification software product for companies developing systems on a chip (SoCs) or integrating intellectual property (IP) blocks.

Aug. 02, 2007 - Validation has included silicon correlation tests on representative design IP such as phase lock loops, focusing on simulation results and postlayout parasitics.

Aug. 01, 2007 - Tata Elxsi Will Provide Turnkey LSI and System Design Services for Tensilica's Audio and Video Processor Customers

Jul. 25, 2007 - Cadence Design Systems today announced that CES Design Services has deployed Cadence® assertion-based verification IP (ABVIP) to maximize quality and minimize completion time for its client designs and for its own standard IP blocks

Jul. 25, 2007 - Global Unichip today announced the success of delivering the ARM926 solution with a 400MHz performance on TSMC 0.13G process to a leading developer of navigation processor solutions for mobile navigation devices. Same effort has achieved a 650MHz performance on the ARM1136 solution with TSMC 0.13LV ...

Jul. 24, 2007 - Arasan is gaining market share rapidly by offering China customers a special set of incentives on Silicon IP along with the critical elements of a total USB solution that they require to efficiently integrate USB into a SoC/ASIC. Arasans ability to provide onsite support and integration services in ...

Jul. 19, 2007 - Ridgetop Group reported it has received a purchase order from Raytheon Missile Systems (RMS), Tucson, AZ, to design, build, program, and deliver Solder-Joint Built-in-Self-Test™ (SJ BIST™) evaluation and demonstration kits. The demonstration kits will allow RMS to evaluate SJ BIST for possible inclusion ...

Jul. 23, 2007 - The SJ-BIST product consists of a Verilog softcore that is synthesizable into a customer’s FPGA, along with full documentation and application assistance. The product is a new addition to Ridgetop’s InstaBIST™ family of built-in self test IP solutions. IP Licenses are available.

Jul. 23, 2007 - As compared to traditional RTL-based design methods, the SystemC design methodology described can yield significant savings in overall design cycle time anywhere from 1/3 to 1/2. The guide includes examples of design blocks in excess of 3 million gates being designed using SystemC descriptions. The ...

Jul. 18, 2007 - Chipidea today announced the industry’s first Flexible Mixed-Signal IP Platform Architecture™ (FLEMIA), a highly innovative approach to integrating multiple blocks of analog functionality into a single chip to streamline electronic system design. Leveraging Chipidea’s extensive, silicon-proven ...

Jul. 12, 2007 - ATDF and UMC will focus on specialty technologies - including nanotech and memory designs - that originate with small companies, university labs, and other organizations. ATDF will evaluate the technologies that match UMC's manufacturability criteria, while UMC will work with select innovators to evaluate ...

Jul. 09, 2007 - From its office in the Beijing IC Design Park, which is supported by the Beijing Municipal government to help foster more IC design activity in the region, Improv will offer extensive pre- and post-sales technical support for its complete Jazz-based tool and IP product portfolio Improv

Jul. 09, 2007 - The Novas platform unifies the languages, abstractions and tools needed to cut in half the time it takes to understand and debug design behavior starting from system-level specification through silicon implementation. Novas' latest advancements are expected to deliver three to ten times more performance ...

Jul. 09, 2007 - OCP-IP today announced their support of Cadence’s Assertion Based Verification IP (ABVIP) for the development and verification of the OCP protocol. OCP’s ascendance as the system architecture “backbone” within increasingly complex consumer and portable designs has driven the need for improved ...

Jun. 28, 2007 - Synopsys today announced that it has teamed with UMC to port the Synopsys DesignWare USB 2.0, PCI Express, SATA and XAUI PHY semiconductor intellectual property (IP) to UMC's 90-nanometer (nm) and 65-nm technologies

Jun. 20, 2007 - Encounter RTL Compiler with global synthesis enables Tensilica customers to achieve smaller, faster and lower-power implementations for microprocessor designs using Tensilica IP

Jun. 19, 2007 - The DesignWare VPXA3 Virtual Platform provides software engineers with a high-speed, pre-silicon software execution environment that allows the development of system-on-chip- (SoC) related software before hardware is available. The Virtual Platform technology enables the creation of a software model ...

Jun. 18, 2007 - Recognizing the semiconductor industry's need for an open market approach to providing comprehensive analog intellectual property (IP) solutions, Chipidea®, the world leader in analog/mixed-signal subsystems and IP, today announced it has created the first Analog IP Foundry(TM) to help customers circumvent ...

Jun. 12, 2007 - Chartered Semiconductor Manufacturing and Tezzaron Semiconductor today announced that Chartered is beginning to ramp production of Tezzaron's unique ultra high-speed memory chips.

Jun. 14, 2007 - With the complexity of both hardware and software growing significantly, the challenge of designing and testing software earlier in the design process is becoming an increasingly significant factor, especially in cases where the hardware environment may be extremely complex and/or not yet available.

Jun. 06, 2007 - The KAIST (Korea Advanced Institute of Science and Technology) has licensed the Xtensa configurable processor to develop multimedia SOC (system-on-chip) designs.

Jun. 05, 2007 - Focusing on the methodology described in the Verification Methodology Manual (VMM) for SystemVerilog book, the VMM Catalyst Program is open to electronic design automation (EDA) vendors, silicon and verification intellectual property (IP) companies, and training and service providers to benefit mutual ...

Jun. 04, 2007 - This is the second node, following 65nm, where the alliance partners have driven comprehensive DFM solutions, which marry technology and tool support from leading EDA and DFM suppliers with manufacturing data and models from the Common Platform technology foundries to help ensure the success of chip ...

Jun. 04, 2007 - Adaptive Verification IP combines the time-to-market advantages of automated verification with the quality of in-context, knowledge-based verification that was previously only possible manually. Adaptive Verification IP complements existing random or directed-random methods with a powerful new approach ...

Jun. 04, 2007 - Reference Flow 8.0 supports TSMC's 45nm process technology with advanced standard cell, standard I/O, and SRAM compiler. Key features address new design challenges at 45nm, including statistical timing analysis for intra-die variation, automated DFM hot-spot fixing, and new dynamic low-power design ...