Dec. 07, 2020 - With the growing chip complexity observed in many market segments, in addition to a need for longer battery life, SoC design teams are forced to adopt advanced power management techniques to improve the energy-efficiency of their devices.

Nov. 02, 2020 - Cadence achieves recognition for joint development of N3 design infrastructure, 3D-IC design productivity solution, timing signoff in the cloud design solution and DSP IP

Nov. 03, 2020 - Movellus’ fully synthesizable and quickly customizable PLLs/DLLs are available to GF customers around the world with the goal of further enabling their designs and ultimately reducing their time-to-market.

Oct. 28, 2020 - Synopsys, Inc. (Nasdaq: SNPS) today announced the release of the 3-nanometer (nm) gate-all-around (GAA) AMS Design Reference Flow, which provides designers a complete front-to-back design methodology for designing analog and mixed-signal circuits using the Synopsys Custom Design Platform.

Oct. 22, 2020 - Synopsys, Inc. (Nasdaq: SNPS) today announced that its 3DIC Compiler solution enabled Samsung Foundry to design, implement and tape out a complex 5-nanometer SoC featuring eight high-bandwidth memories (HBMs) in a single package.

Oct. 22, 2020 - Collaboration with IBM Research's AI Hardware Center Addresses the Challenges of Developing New AI Chip Architectures with Innovative Design Methodologies

Oct. 14, 2020 - Synopsys, Inc. (Nasdaq: SNPS) and Samsung Foundry today announced the release of a validated automotive reference flow to streamline SoC hardware design for in-system test, implementation, verification, timing and physical signoff for ISO 26262 compliance.

Oct. 07, 2020 - Movellus announced today that Everactive has adopted Movellus’ ultra-low power clocking solution for its batteryless Machine Health Monitoring (MHM) IoT product. Everactive’s core SoC is clocked by Movellus ultra low power PLL.

Oct. 07, 2020 - martDV™ Technologies, the Proven and Trusted choice for Design and Verification intellectual property (IP), today unveiled SmartConf testbench generator, an add-on automation tool to its extensive Verification IP portfolio.

Sep. 24, 2020 - Synopsys today announced its latest collaboration with GLOBALFOUNDRIES (GF®) to drive productivity and power, performance, and area (PPA) enhancements for mutual customers deploying the Synopsys Fusion Compiler™ RTL-to GDSII product – the industry's only single data model and golden-signoff enabled ...

Sep. 22, 2020 - SmartDV™ Technologies once again is the first company to ship Verification intellectual property (IP) to support MIPI A-PHY v1.0, the industry-standard, long-reach serializer-deserializer (SerDes) physical layer interface, delivering it as the MIPI Alliance announced availability.

Aug. 17, 2020 - SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced OpenFive, a self-contained and autonomous business unit to capture the opportunity offered by enabling customizable, silicon-focused solutions with differentiated-IP.

Aug. 17, 2020 - Movellus today announced that the company was named an EETimes’ Silicon 100 emerging company to watch. Movellus was noted for its technology enabling the use of digital design and verification tools to quickly implement analog functionality.

Jul. 22, 2020 - Imperas Software today announced that OpenHW Group has established the CORE-V processor verification test bench using the Imperas RISC-V reference model to deliver quality IP cores to the OpenHW Group ecosystem and the open source hardware community.

Jul. 20, 2020 - SmartDV™ Technologies and Aldec today inked an agreement linking SmartDV’s Verification IP with Aldec’s Riviera-PRO™ high-performance simulation and debugging tool.

Jul. 16, 2020 - EasyIC Design is proud to be celebrating its 10-year Anniversary in 2020. This engineering consultancy and IP company was founded in Bucharest in 2010 by two engineers and friends, Dragos Vlad and Misu Preda. Their vision was to create a new kind of technical company in Romania.

Jul. 16, 2020 - Arm Research is working with the U.S. Defense Advanced Research Projects Agency (DARPA) on the Automatic Implementation of Secure Silicon (AISS) program.

Jul. 07, 2020 - SmartDV™ Technologies, the Proven and Trusted choice for Design and Verification Intellectual Property (IP), broadens its support for the Arm® AMBA® protocol with availability of Verification IP solutions for AMBA CHI, CXS and LPI protocols.

Jun. 29, 2020 - Synopsys today announced it has signed a multi-year agreement with Arm for the purpose of accelerating design and verification of Arm®-based system-on-chips (SoCs) for mutual customers.

Jun. 25, 2020 - Synopsys, Inc. (Nasdaq: SNPS) today announced that the Defense Advanced Research Projects Agency (DARPA) has selected Synopsys as a prime contractor for the Automatic Implementation of Secure Silicon (AISS) program.

Jun. 25, 2020 - Bamboo Systems, a provider of transformative Arm®-based servers, today announced the availability of its newest systems, the B1000N Series, based on a revolutionary new system architecture, Bamboo PANDA™.

Jun. 16, 2020 - Agile Analog, a leading provider of semiconductor analog IP, today announced that they have worked with EnSilica, a leading fabless design house focused on custom ASIC design and supply services, to both fabricate and test their latest analog IP products, and to validate that their advanced product ...

Jun. 03, 2020 - Cadence today announced that its digital full flow and custom/analog tool suites have been further enhanced to deliver optimal results on TSMC’s N6 and N5 process technologies.

Jun. 01, 2020 - Cadence today announced that Ambarella, Inc. has adopted the Cadence® Clarity™ 3D Solver for design of their next-generation AI vision processors.

May. 12, 2020 - Agile Analog, a leading provider of semiconductor analog IP, today announced Palma Ceia SemiDesign, a provider of communication chips and IP for WiFi HaLow and Cellular NB-IoT applications, has selected Agile Analog’s data converter and power management IP for its next-generation of WiFi and cellular ...

Apr. 21, 2020 - Imperas Software today announced that Mellanox Technologies, a leading supplier of high-performance, end-to-end smart interconnect solutions for datacenter servers and storage systems, has selected the Imperas advanced hardware verification of RISC-V processors.

Apr. 15, 2020 - UltraSoC and Agile Analog today announced a collaboration that aims to deliver the industry’s most comprehensive hardware-based cybersecurity infrastructure by combining UltraSoC’s embedded on-chip analytics with Agile Analog’s advanced on-chip analog monitoring IP.

Apr. 07, 2020 - Mirabilis Design announced today that they will be conducting free training class on Model-based System Simulation and Electronic System-Level Design for all Engineers and students.

Apr. 02, 2020 - Synopsys today announced its expanded collaboration with Broadcom Inc. for the creation of semiconductor solutions using Synopsys' Fusion Design Platform™ to address a host of design challenges at 7nm and beyond.

Mar. 16, 2020 - eInfochips launches DAeRT (DFT Automated Execution and Reporting Tool) - an automated framework for the semiconductor industry, which provides a complete solution for DFT, starting from architecture to implementation for any ASIC (Application Specific Integrated Circuit).

Mar. 05, 2020 - Tessolve consolidated its position as a leading multinational engineering solution provider with the acquisition of Test & Verification Solutions (T&VS). Tessolve, a part of the Hero Electronics group will now be in a better position to provide full turnkey VLSI design services from RTL to GDSII.

Mar. 04, 2020 - Defacto’s latest Release STAR 8.0 helps to lower the complexity of typical SoC Integration design flows where several sources of design information are required to start building an SoC, including design descriptions (mixed RTL code, gate-level netlist, physical) and design collaterals (power intent, ...

Feb. 24, 2020 - Imperas Software today announced a collaboration with Mentor, a Siemens business, on the latest hardware Design Verification (DV) Flow for RISC-V processor implementations, to ensure an easy to use reference methodology is available to processor developers, users and adopters across the RISC-V ecosystem. ...

Jan. 07, 2020 - Siemens Digital Industries Software today announced a partnership with global semiconductor IP leader Arm, that will bring leading edge IP, methodologies, processes and tools together to help automakers, integrators and suppliers collaborate, design and bring to market their next-generation platforms ...

Dec. 18, 2019 - Aldec has added features to its Riviera-PRO functional verification platform that provide further support when working with the latest version of VHDL (2018) as well as the 2019.09.02 release of the Universal VHDL Verification Methodology (UVVM).

Nov. 26, 2019 - Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced the release of the latest update to the RISC-V compliance test suite for RV32I base RISC-V configuration.

Nov. 21, 2019 - SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP), today announced its broad portfolio of portable, platform-independent VIP ensures a thorough and seamless coverage-driven verification flow with no coverage gaps between simulation, emulation or formal ...

Nov. 19, 2019 - EasyIC Design announced today that it has been accepted as a member of the Arm® Approved Design Partner Program.

Nov. 18, 2019 - Synopsys today announced that Samsung Electronics has adopted the Synopsys Custom Design Platform, based on the Custom Compiler™ design environment, to design IP for its 5-nanometer (nm) Low-Power Early (LPE) process with Extreme Ultraviolet (EUV) lithography technology.

Nov. 06, 2019 - Today, we are excited to unveil the OpenTitan silicon root of trust (RoT) project, a new effort built using the successful collaborative engineering model created by lowRISC in partnership with Google and other commercial and academic partners.