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QThink Certified as inSilicon Authorized Design Center
Sep. 17, 2001 - QThink Certified as inSilicon Authorized Design Center -
Virage Logic and ATMOS Corporation Launch Joint Sales of Silicon-Proven, Compiled Embedded DRAM in TSMC's Standard Logic Process
Oct. 10, 2001 - Virage Logic and ATMOS Corporation Launch Joint Sales of Silicon-Proven, Compiled Embedded DRAM in TSMC's Standard Logic Process -
ARM Discloses Technical Details Of Extendible PrimeXsys Wireless Platform
Oct. 17, 2001 - ARM Discloses Technical Details Of Extendible PrimeXsys Wireless Platform -
SoC test requirements debated <!-- verification -->
Nov. 02, 2001 - SoC test requirements debated <!-- verification --> -
Artisan tips its 0.1-micron library
Nov. 05, 2001 - Artisan tips its 0.1-micron library -
MoSys 1T-SRAM Macros Now Proven in Multiple Versions of TSMC'S Standard and Triple-Oxide 0.13-Micron Logic Processes
Nov. 12, 2001 - MoSys 1T-SRAM Macros Now Proven in Multiple Versions of TSMC'S Standard and Triple-Oxide 0.13-Micron Logic Processes -
EDA vendors fall short on innovation, speaker says <!-- verification -->
Nov. 14, 2001 - EDA vendors fall short on innovation, speaker says <!-- verification --> -
Open SystemC focus shifts to modelling systems <!-- verification -->
Nov. 14, 2001 - Open SystemC focus shifts to modelling systems <!-- verification --> -
Tool vendors Synplicity Inc. and Forte Design Systems Inc. bring system-level tools to PLD masses
Nov. 19, 2001 - Tool vendors Synplicity Inc. and Forte Design Systems Inc. bring system-level tools to PLD masses -
Open SystemC group considers its next steps <!-- verification -->
Nov. 20, 2001 - Open SystemC group considers its next steps <!-- verification --> -
Taiwan confronts SoC obstacles
Nov. 20, 2001 - Taiwan confronts SoC obstacles -
Tera Systems' Tool Adopted by NEC Electronics for RTL Design Closure and Virtual Prototyping <!-- verification -->
Nov. 26, 2001 - Tera Systems' Tool Adopted by NEC Electronics for RTL Design Closure and Virtual Prototyping -
STARC Selects Verisity's e Verification Language for IP Reuse <!-- verification --> --> "Arial,Helvetica" size=-1 > Headline News
Dec. 03, 2001 - STARC Selects Verisity's e Verification Language for IP Reuse <!-- verification --> --> "Arial,Helvetica" size=-1 > Headline News -
Atmel Introduces Second Generation EDA Tool For Programmable System-On-Chips
Dec. 10, 2001 - Atmel Introduces Second Generation EDA Tool For Programmable System-On-Chips -
Sun Microsystems Standardizes on LogicVision's Embedded Test Solutions
Dec. 11, 2001 - Sun Microsystems Standardizes on LogicVision's Embedded Test Solutions -
Verisity And eInfochips Deliver PCI-X <i>e</i> Verification Component
Dec. 17, 2001 - Verisity And eInfochips Deliver PCI-X <i>e</i> Verification Component -
ARM and Verisity Advance IP Verification and Validation
Jan. 07, 2002 - ARM and Verisity Advance IP Verification and Validation -
India hopes to step from software to product design
Jan. 11, 2002 - India hopes to step from software to product design -
iRoC Releases Robust SPARC Test Report
Jan. 28, 2002 - iRoC Releases Robust SPARC Test Report -
CoWare and Verisity Provide a Unified System-Level Design Flow With a Re-usable Testbench <!-- verification -->
Jan. 28, 2002 - CoWare and Verisity Provide a Unified System-Level Design Flow With a Re-usable Testbench <!-- verification --> -
Sagantec says tool finds errors others miss
Jan. 28, 2002 - Sagantec says tool finds errors others miss
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