Mar. 05, 2020 - Tessolve consolidated its position as a leading multinational engineering solution provider with the acquisition of Test & Verification Solutions (T&VS). Tessolve, a part of the Hero Electronics group will now be in a better position to provide full turnkey VLSI design services from RTL to GDSII.

Mar. 04, 2020 - Defacto’s latest Release STAR 8.0 helps to lower the complexity of typical SoC Integration design flows where several sources of design information are required to start building an SoC, including design descriptions (mixed RTL code, gate-level netlist, physical) and design collaterals (power intent, ...

Feb. 24, 2020 - Imperas Software today announced a collaboration with Mentor, a Siemens business, on the latest hardware Design Verification (DV) Flow for RISC-V processor implementations, to ensure an easy to use reference methodology is available to processor developers, users and adopters across the RISC-V ecosystem. ...

Jan. 07, 2020 - Siemens Digital Industries Software today announced a partnership with global semiconductor IP leader Arm, that will bring leading edge IP, methodologies, processes and tools together to help automakers, integrators and suppliers collaborate, design and bring to market their next-generation platforms ...

Dec. 18, 2019 - Aldec has added features to its Riviera-PRO functional verification platform that provide further support when working with the latest version of VHDL (2018) as well as the 2019.09.02 release of the Universal VHDL Verification Methodology (UVVM).

Nov. 26, 2019 - Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced the release of the latest update to the RISC-V compliance test suite for RV32I base RISC-V configuration.

Nov. 21, 2019 - SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP), today announced its broad portfolio of portable, platform-independent VIP ensures a thorough and seamless coverage-driven verification flow with no coverage gaps between simulation, emulation or formal ...

Nov. 19, 2019 - EasyIC Design announced today that it has been accepted as a member of the Arm® Approved Design Partner Program.

Nov. 18, 2019 - Synopsys today announced that Samsung Electronics has adopted the Synopsys Custom Design Platform, based on the Custom Compiler™ design environment, to design IP for its 5-nanometer (nm) Low-Power Early (LPE) process with Extreme Ultraviolet (EUV) lithography technology.

Nov. 06, 2019 - Today, we are excited to unveil the OpenTitan silicon root of trust (RoT) project, a new effort built using the successful collaborative engineering model created by lowRISC in partnership with Google and other commercial and academic partners.

Nov. 04, 2019 - UltraSoC has announced a partnership with Europractice, to bring UltraSoC debug and trace IP for open source RISC-V development to a wider community and to make the company’s IP more readily and freely available for academic ASIC development.

Oct. 24, 2019 - 3 papers by Veriest experts were selected for presentation at Europe's leading Design & Verification conference, to take place in Munich, 29-30, October.

Oct. 17, 2019 - SmartDV™ Technologies will highlight its range of VIP at DVCon Europe (Booth #404) and demonstrate its Smart ViPDebug™, a protocol debugger that reduces debug time by rapidly identifying violations

Oct. 16, 2019 - sureCore Limited, a provider of low power SRAM products and custom memory design services, today announced that its PowerMiser low power SRAM IP is now available for designs targeting the Samsung 28nm FDS process.

Oct. 01, 2019 - SmartDV™ Technologies today announced support for Verilator, the free, open-source hardware description language (HDL) simulator, becoming the first Verification Intellectual Property (VIP) provider to do so.

Sep. 30, 2019 - The explosion of intelligent IoT devices and connected vehicles, supported by a fast-growing communication and processing infrastructure, is creating an exponential demand for energy. If we want to properly use our limited resources, energy saving must be considered as our main innovation focus.

Sep. 25, 2019 - Cadence today announced that its digital and signoff full flow and custom/analog tools have achieved certification on TSMC’s N6 and N5/N5P process technologies.

Sep. 17, 2019 - SmartDV™ Technologies today announced its Design IP for the Ethernet Time-Sensitive Networking (TSN) protocol, an update to the IEEE standard for time-sensitive transmission of data over Ethernet networks.

Sep. 11, 2019 - SmartDV TileLink Verification IP for RISC-V Based Systems, Smart ViPDebug Protocol Debugger at DVCon India

Sep. 10, 2019 - Agile Analog, a Cambridge based Analog IP company, today announced the appointment of Sir Hossein Yassaie as Non-Executive Director to their Board of Directors.

Sep. 06, 2019 - Imagination Technologies announces today that it is expanding its business with a tailored consultancy, hosting and deployment service for design and verification, called IMG Edge.

Aug. 27, 2019 - sureCore Limited today announced that it has opened a new Low Power Design Service that offers its concept-to-tape-out low power mixed-signal design expertise to ASIC developers.

Aug. 14, 2019 - SmartDV™ Technologies will feature the first commercially available OpenCAPI Verification IP compatible with the OpenCAPI 3.0 and 3.1 standard at the OpenPower Summit.

Jul. 30, 2019 - Agile Analog, a Cambridge-based Analog IP company, announces it has successfully been awarded funding from Innovate UK, the UK’s innovation agency, to accelerate their new product development.

Jul. 22, 2019 - Cadence today unveiled the Cadence® Conformal® Litmus, the next-generation solution that provides constraints signoff and clock domain crossing (CDC) signoff, reducing overall design cycle times and enhancing the quality of silicon in complex system-on-chip (SoC) designs.

Jul. 16, 2019 - SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP), today announced it expanded its portfolio with availability of DisplayPort 2.0 VIP, a digital display interface used to connect a video source to a display or monitor.

Jun. 25, 2019 - SmartDV™ Technologies added new Verification IP to support the OpenCAPI standard aimed at boosting the performance of data center servers tasked with analyzing large amounts of data.

Jun. 05, 2019 - Synopsys today announced that Faraday Technology Corporation, a leading fabless ASIC and IP provider, has adopted Synopsys' SpyGlass® Design Handoff Kit. Faraday has deployed the SpyGlass Design Handoff Kit to ensure ASIC designs meet design quality requirements before initiating ASIC design service ...

Jun. 04, 2019 - Cadence today announced the Cadence® Spectre® X Simulator, a massively parallel circuit simulator designed to provide up to 10X performance gains, while maintaining the golden accuracy customers have come to expect from 25 years of Spectre industry leadership in analog, mixed-signal and RF applications. ...

Jun. 03, 2019 - Silvaco today announced that it is providing an open-source, 15nm standard-cell library to Silicon Integration Initiative. The library is available to Si2 members and universities at no fee under the Apache-2.0 open source license agreement.

May. 31, 2019 - At the Design Automation Conference (DAC), True Circuits will showcase its high performance, silicon proven DDR 4/3 PHY hard macro with state-of-the-art tuning and training, and remarkable physical flexibility to adapt to each customer’s die floorplan and package.

May. 23, 2019 - Cadence Design Systems today announced that Thinci has deployed the full Cadence® Verification Suite to accelerate the design and verification of its machine learning and artificial intelligence (AI) system-on-chip (SoC) designs.

May. 23, 2019 - SmartDV™ Technologies today announced immediate availability of its latest Verification Intellectual Property (IP) to support Compute Express Link (CXL), a new high-speed CPU-to-device and CPU-to-memory interconnect to accelerate the performance of next-generation data centers.

May. 23, 2019 - SmartDV™ Technologies today unveiled Verification IP for Ethernet Time-Sensitive Networking (TSN), an update to the IEEE standard for time-sensitive transmission of data over Ethernet networks.

May. 16, 2019 - SmartDV™ Technologies today unveiled Smart ViPDebug™, a protocol debugger that reduces debug time by rapidly identifying violations and reducing the time needed to find the cause of violations through its linked waveform and transaction database views.

May. 15, 2019 -

May. 13, 2019 - Agile Analog, a Cambridge analog IP company, announces it has closed its latest Pre-A funding round with Delin Ventures, firstminute Capital and MMC Ventures for $5M. Founded in 2017, Agile Analog will use the funding to expand the existing engineering team in Cambridge and deliver analog IP products ...

May. 09, 2019 - SmartDV™ Technologies today named HyperSilicon Co. Ltd. its exclusive sales representative in China. HyperSilicon is a technical sales and support organization based in Beijing, China, with a 30-member team of IP, system-on-chip (SoC), application specific integrated circuit (ASIC) and field-programmable ...

Apr. 24, 2019 - Synopsys, Inc. today announced that the Synopsys Design Platform has been certified for TSMC's latest System-on-Integrated-Chips (TSMC-SoIC™) 3D chip stacking technology.

Apr. 24, 2019 - Full suite of Cadence digital and signoff, custom/analog, and IC package and PCB analysis tools optimized for TSMC SoIC chip stacking technology