Nov. 04, 2019 - UltraSoC has announced a partnership with Europractice, to bring UltraSoC debug and trace IP for open source RISC-V development to a wider community and to make the company’s IP more readily and freely available for academic ASIC development.

Oct. 24, 2019 - 3 papers by Veriest experts were selected for presentation at Europe's leading Design & Verification conference, to take place in Munich, 29-30, October.

Oct. 17, 2019 - SmartDV™ Technologies will highlight its range of VIP at DVCon Europe (Booth #404) and demonstrate its Smart ViPDebug™, a protocol debugger that reduces debug time by rapidly identifying violations

Oct. 16, 2019 - sureCore Limited, a provider of low power SRAM products and custom memory design services, today announced that its PowerMiser low power SRAM IP is now available for designs targeting the Samsung 28nm FDS process.

Oct. 01, 2019 - SmartDV™ Technologies today announced support for Verilator, the free, open-source hardware description language (HDL) simulator, becoming the first Verification Intellectual Property (VIP) provider to do so.

Sep. 30, 2019 - The explosion of intelligent IoT devices and connected vehicles, supported by a fast-growing communication and processing infrastructure, is creating an exponential demand for energy. If we want to properly use our limited resources, energy saving must be considered as our main innovation focus.

Sep. 25, 2019 - Cadence today announced that its digital and signoff full flow and custom/analog tools have achieved certification on TSMC’s N6 and N5/N5P process technologies.

Sep. 17, 2019 - SmartDV™ Technologies today announced its Design IP for the Ethernet Time-Sensitive Networking (TSN) protocol, an update to the IEEE standard for time-sensitive transmission of data over Ethernet networks.

Sep. 11, 2019 - SmartDV TileLink Verification IP for RISC-V Based Systems, Smart ViPDebug Protocol Debugger at DVCon India

Sep. 10, 2019 - Agile Analog, a Cambridge based Analog IP company, today announced the appointment of Sir Hossein Yassaie as Non-Executive Director to their Board of Directors.

Sep. 06, 2019 - Imagination Technologies announces today that it is expanding its business with a tailored consultancy, hosting and deployment service for design and verification, called IMG Edge.

Aug. 27, 2019 - sureCore Limited today announced that it has opened a new Low Power Design Service that offers its concept-to-tape-out low power mixed-signal design expertise to ASIC developers.

Aug. 14, 2019 - SmartDV™ Technologies will feature the first commercially available OpenCAPI Verification IP compatible with the OpenCAPI 3.0 and 3.1 standard at the OpenPower Summit.

Jul. 30, 2019 - Agile Analog, a Cambridge-based Analog IP company, announces it has successfully been awarded funding from Innovate UK, the UK’s innovation agency, to accelerate their new product development.

Jul. 22, 2019 - Cadence today unveiled the Cadence® Conformal® Litmus, the next-generation solution that provides constraints signoff and clock domain crossing (CDC) signoff, reducing overall design cycle times and enhancing the quality of silicon in complex system-on-chip (SoC) designs.

Jul. 16, 2019 - SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP), today announced it expanded its portfolio with availability of DisplayPort 2.0 VIP, a digital display interface used to connect a video source to a display or monitor.

Jun. 25, 2019 - SmartDV™ Technologies added new Verification IP to support the OpenCAPI standard aimed at boosting the performance of data center servers tasked with analyzing large amounts of data.

Jun. 05, 2019 - Synopsys today announced that Faraday Technology Corporation, a leading fabless ASIC and IP provider, has adopted Synopsys' SpyGlass® Design Handoff Kit. Faraday has deployed the SpyGlass Design Handoff Kit to ensure ASIC designs meet design quality requirements before initiating ASIC design service ...

Jun. 04, 2019 - Cadence today announced the Cadence® Spectre® X Simulator, a massively parallel circuit simulator designed to provide up to 10X performance gains, while maintaining the golden accuracy customers have come to expect from 25 years of Spectre industry leadership in analog, mixed-signal and RF applications. ...

Jun. 03, 2019 - Silvaco today announced that it is providing an open-source, 15nm standard-cell library to Silicon Integration Initiative. The library is available to Si2 members and universities at no fee under the Apache-2.0 open source license agreement.

May. 31, 2019 - At the Design Automation Conference (DAC), True Circuits will showcase its high performance, silicon proven DDR 4/3 PHY hard macro with state-of-the-art tuning and training, and remarkable physical flexibility to adapt to each customer’s die floorplan and package.

May. 23, 2019 - Cadence Design Systems today announced that Thinci has deployed the full Cadence® Verification Suite to accelerate the design and verification of its machine learning and artificial intelligence (AI) system-on-chip (SoC) designs.

May. 23, 2019 - SmartDV™ Technologies today announced immediate availability of its latest Verification Intellectual Property (IP) to support Compute Express Link (CXL), a new high-speed CPU-to-device and CPU-to-memory interconnect to accelerate the performance of next-generation data centers.

May. 23, 2019 - SmartDV™ Technologies today unveiled Verification IP for Ethernet Time-Sensitive Networking (TSN), an update to the IEEE standard for time-sensitive transmission of data over Ethernet networks.

May. 16, 2019 - SmartDV™ Technologies today unveiled Smart ViPDebug™, a protocol debugger that reduces debug time by rapidly identifying violations and reducing the time needed to find the cause of violations through its linked waveform and transaction database views.

May. 15, 2019 -

May. 13, 2019 - Agile Analog, a Cambridge analog IP company, announces it has closed its latest Pre-A funding round with Delin Ventures, firstminute Capital and MMC Ventures for $5M. Founded in 2017, Agile Analog will use the funding to expand the existing engineering team in Cambridge and deliver analog IP products ...

May. 09, 2019 - SmartDV™ Technologies today named HyperSilicon Co. Ltd. its exclusive sales representative in China. HyperSilicon is a technical sales and support organization based in Beijing, China, with a 30-member team of IP, system-on-chip (SoC), application specific integrated circuit (ASIC) and field-programmable ...

Apr. 24, 2019 - Synopsys, Inc. today announced that the Synopsys Design Platform has been certified for TSMC's latest System-on-Integrated-Chips (TSMC-SoIC™) 3D chip stacking technology.

Apr. 24, 2019 - Full suite of Cadence digital and signoff, custom/analog, and IC package and PCB analysis tools optimized for TSMC SoIC chip stacking technology

Apr. 22, 2019 - Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it has collaborated with TSMC to enable customers’ production delivery of next-generation system-on-chip (SoC) designs for mobile, high-performance computing (HPC), 5G and artificial intelligence (AI) applications on TSMC’s 5nm FinFET ...

Apr. 22, 2019 - Synopsys, Inc. (Nasdaq: SNPS) today announced that Desay SV has adopted its Virtualizer™ virtual prototyping solution to accelerate software development of next-generation automotive systems.

Apr. 18, 2019 - The program focuses on delivering Synopsys Virtualizer™ Development Kits (VDKs) for the ST Stellar family of automotive multicore microcontrollers (MCUs), enabling companies to accelerate the development of automotive electronic systems by enabling the move from physical to virtual testing.

Apr. 16, 2019 - Samsung Electronics today announced that its 5-nanometer (nm) FinFET process technology is complete in its development and now is ready for customers’ samples. By adding another cutting-edge node to its extreme ultraviolet (EUV)-based process offerings, Samsung is proving once again its leadership ...

Apr. 03, 2019 - TSMC today announced delivery of the complete version of its 5 nanometer (nm) design infrastructure within the Open Innovation Platform® (OIP). This full release enables 5nm systems-on-chip (SoC) designs in next-generation advanced mobile and high-performance computing (HPC) applications, targeting ...

Apr. 01, 2019 - Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the Cadence® Innovus™ Implementation System and Quantus™ Extraction Solution are now enabled for the Samsung Foundry Gate-All-Around (GAA) technology.

Mar. 28, 2019 - Cadence today announced that it is working with Northrop Grumman on advanced-node system-on-chip (SoC) projects, enabling the delivery of high-quality, high-performance SoCs. Cadence® system and verification, digital and signoff, custom/analog and packaging tools, as well as IP solutions, have supported ...

Mar. 14, 2019 - Synopsys today announced that Renesas Electronics Corporation has deployed Synopsys' Fusion Compiler™ RTL-to-GDSII implementation solution for its high-performance automotive system-on-chips (SoCs) and mission-critical microcontrollers (MCUs) to accelerate broad market access to next-generation automotive ...

Feb. 19, 2019 - GLOBALFOUNDRIES (GF) and Dolphin Integration, a leading provider of semiconductor IP, today announced a collaboration to develop a series of adaptive body bias (ABB) solutions to improve the energy efficiency and reliability of system-on-chip (SoC) on GF’s 22nm FD-SOI (22FDX®) process technology ...

Jan. 23, 2019 - Inomize, a world leader of ASIC design services was selected by HP Indigo to develop an ASIC solution for their next generation of high-resolution industrial presses.