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I2C IP Listing

557 IP Cores (41 - 80)

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I2C Slave with AHB Master Bridge (I2C2AHB)

The DB-I2C-S-AHB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & control registers (and thus no local host ...

41
I2C IO Pad Set

The I2C library provides the bidirectional I/O for two-line serial communication per Rev. 4 of the I2C-bus industry specification. The design is compatible with Standard-mode, Fast-mode, and ...

42
I2C IO Pad Set

Product Features ; • Supported I2C operating modes: ; o Standard-mode (Sm) – 100 Kbps data rate ; o Fast mode (Fm) – 400 Kbps data rate ; o Fast mode (Fm+) – 3.4 Mbps data rate ; • ...

43
I2C I/O Pad Set

The I2C libraries provide the bidirectional I/O for two-line serial communication per Rev. 4 of the I2Cbus industry specification. The design is compatible with Standard-mode, Fast-mode, and ...

44
I2C I/O Pad Set

The I2C library provides open-drain bi-directional I/O cells designed for the I2C two-line interface. It is compliant with the I2C-bus specification – UMC10204 I2C-bus specification and user ...

45
I2C IO Pad Set

The I2C library provides open-drain bi-directional I/O cells designed for the I2C two-line interface. It is compliant with the I2C-bus specification – UMC10204 I2C-bus specification and user ...

46
I2C I/O Pad Set

The I2C libraries provide the bidirectional I/O for two-line serial communication per Rev. 4 of the I2Cbus industry specification. The design is compatible with Standard-mode, Fast-mode, and ...

47
I2C MAster Slave

The MI2CMS macro implements a synchronous single-chip I2C Master and Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is carried out on a byte-wise basis using ...

48
I2C Master

The MI2CM macro implements a synchronous single-chip I2C Master only Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is carried out on a byte-wise basis using interrupt ...

49
I2C Slave

The MI2CS macro implements a synchronous single-chip I2C Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is carried out on a byte-wise basis using interrupt ...

50
I2C Master Serial Interface Controller

Master serial interface compatible with the popular Philips® I2C standard. Features a simple command interface and permits multiple I2C slaves to be controlled directly from your FPGA, CPLD ...

51
I2C Slave Serial Interface Controller

Slave serial interface compatible with the popular Philips® I2C standard. Permits an I2C Master to communicate with your FPGA, CPLD or ASIC device. Auto-detects standard (100 kbits/s), fast ...

52
UART to I2C Bridge Controller

Allows simple connectivity between a UART 2-wire port (Tx/Rx) and an I2C compatible bus. Allows simple programming and debug of an I2C device using a remote PC.

53
I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)

The Digital Blocks DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AXI system Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard ...

54
I2C Master and Slave

I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring occasional communication ...

55
Serial Controller Interface

The SCI Slave is a synthesizable, flexible, and structured VHDL implementation of a Serial Controller Interface (SCI) that uses a two-wire bus for communicating between integrated circuits or ...

56
I2C Bus Interface

The serial controller interface (Single Master) core uses a two-wire bus for communicating between integrated circuits or standard peripherals like smart LCDs and keypads. The core contains ...

57
I2C Host / Device Bus Controller

The synchronous I2C interface is a block that interconnects an APB bus. The APB - I2C Bridge interfaces to the APB bus on the system side and the I2C bus. The APB interface is used to easily ...

58
I2C Bus Master Controller Core

The I2C-MS core is a controller for the Inter-Integrated Circuit (I2C) bus. The highly configurable core can implement an I2C bus master, slave, or a combined master and slave, and it communicates ...

59
APB Fundamental Peripheral IP, I2C controller, Soft IP

I2C bus interface controller with APB interface.

60
Specialty I2C IO IP, UMC 40nm LP process

UMC 40nm LP/RVT Logic process 1.8V/2.5V/3.3V Multi-Voltage IIC BOAC IO Cell Library.

61
I2C Master Controller w/FIFO (AHB & AHB-Lite Bus)

The Digital Blocks DB-I2C-M-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 APB System Interconnect Fabric to an I2C Bus. ...

62
I2C Master Controller w/FIFO (AXI & AXI-Lite Bus)

The Digital Blocks DB-I2C-M-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AXI System Interconnect Fabric to an I2C Bus. ...

63
I2C Slave Controller with User Register Array / Memory / FIFO / AMBA Interface

The I2C Controller IP Core implements an I2C Slave Controller, with a user parameterized Register Array or Memory (i.e SRAM / FIFO) or any Peripheral connecting on an AHB / APB / AXI / Avalon ...

64
Hs-Mode I2C Controller - 3.4 Mbps, Master w/FIFO

The Hs-Mode I2C Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bus in Hs-Mode (3.4 Mbit/s) / Fast-Mode Plus (1 Mbit/s) / Fast-Mode ...

65
Hs-Mode I2C Controller - 3.4 Mbps, Slave w/FIFO

The Hs-Mode I2C Controller IP Core interfaces user Registers to an I2C Bus or Memory (SDRAM / SRAM / Flash / FIFO) or any Peripheral or CPU connecting through an internal AHB / APB / AXI / Avalon ...

66
I2C Slave Controller - Low Power, Low Noise Config with APB Interface

The Digital Blocks DB-I2C-S-SCL-CLK-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2.0 APB System Interconnect Fabric to an ...

67
I2C Slave Controller w/FIFO (AXI Bus)

The Digital Blocks DB-I2C-S-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 4/3 AXI System Interconnect Fabric to an I2C Bus. ...

68
I2C Slave Controller w/FIFO (APB Bus)

The Digital Blocks DB-I2C-S-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2.0 APB System Interconnect Fabric to an I2C Bus. ...

69
I2C Slave Controller w/FIFO (AHB Bus)

The Digital Blocks DB-I2C-S-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2.0/3.0 AHB System Interconnect Fabric to an I2C ...

70
I2C/SMBus Master/Slave Controller w/FIFO (AXI/AHB/APB)

The Digital Blocks DB-I2C-SMBus-MS-AMBA Controller IP Core is an I2C/SMBus Master/Slave Controller, interfacing a microprocessor via the AMBA AXI, AHB, or APB Bus to an SMBus Interconnect. Both ...

71
I2C Bus Interface - Master

The I2C is a two-wire, bi-directional serial bus, that provides a simple and efficient method of short distance data transmission between many devices. The DI2CM core provides an interface ...

3 Testimonials
Alex Chen, Project Leader of Business Project Department, Faraday Technology Corporation

72
Slave I2C bus controller with FIFO

The DI2CS core provides an interface between a microprocessor / microcontroller and I2C bus. It can work as: - a slave transmitter or - slave receiver depending on a working mode determined ...

3 Testimonials
Shimon Solodkin, Software Group Manager, Yitran Communications Ltd.

73
I2C Bus Interface Slave -Base version

The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many devices. The DI2CSB provides an interface between ...

3 Testimonials
Markus Wettstein, , Zühlke Engineering AG

74
I2C Bus Interface - Master/Slave

The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many devices. The DI2CMS core provides an interface ...

3 Testimonials
Alex Chen, Project Leader of Business Project Department, Faraday Technology Corporation

75
I2C Master/Slave Interface

CoreI2C provides an APB-driven serial interface, supporting I2C, SMBus, and PMBus data transfers. Several Verilog/VHDL parameters are available to minimize FPGA fabric area for a given application. ...

76
I2C Master-Slave-PIO IP Core

The I2C Master/Slave/PIO IP Core is a complete I2C solution offering three modes of operation and support for standard I2C bus transmission speeds. The I2C Master/Slave core provide a generic ...

77
DO-254 I2C Master Serial Interface Controller 1.00a

Master serial interface compatible with the popular Philips® I2C standard. Features a simple command interface and permits multiple I2C slaves to be controlled directly from your FPGA, CPLD ...

78
Two-Wire slave IP for use with the Mentor M8051W and M8051EW

The M2WIS adds two-wire slave capability to M8051W and M8051EW designs. Use of standard synchronous design methodology makes this core simple to integrate into both ASIC and FPGA SoC designs. ...

79
Four-Wire slave IP for use with the Mentor M8051W and M8051EW

The M4WIS adds four-wire slave capability to the M8051W and M8051EW microcontroller designs that are compatible with the I2C Fast protocol. Clock stretching can be achieved under register control ...

80

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