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サノヤスホールディングス IP Listing

18542 IP Cores (7401 - 7440)

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Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process

Vrr=1.2V Vfr=1.0V, input 1.8V, Core type, Power On Reset, UMC 0.18um GII Logic process.

7401
Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process

Vrr=1.2V Vfr=1.0V, input 1.8V, Core type (with Self-Test Circuit), Power On Reset, UMC 0.18um GII Logic process.

7402
Single Port SRAM Compiler IP, 5.6um2 bit cells, Synchronous, UMC 0.18um eFlash/G2 process

UMC 0.18um e-flash GII Logic process synchronous Single Port SRAM memory compiler.

7403
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 65nm SP process

Input 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 65nm SP/RVT Logic process.

7404
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 65nm SP process

Input 20M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 65nm SP/RVT Logic process.

7405
RC Oscillator IP, Output: 50MHz, UMC 65nm SP process

Internal-RC, trimmable fixed frequency 50MHz, Input 0.9V-1.1V, VBG=0.5V, UMC 65nm SP/RVT Logic Low-K process.

7406
RC Oscillator IP, Output: 12KHz, UMC 65nm LL process

Internal-RC, trimmable fixed frequency 12KHz. Input 1.08V-1.32V, UMC 65nm LL Logic/RVT Low-K process.

7407
PLL (Frequency Synthesizer) IP, Input: 25MHz - 500MHz, Output: 1000MHz - 1500MHz, UMC 65nm SP process

Input 25M-500MHz, output 1000M-1500MHz, frequency synthesizable PLL, UMC 65nm SP/RVT process.

7408
DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 65nm SP process

Boosting voltage from 3.3V to 5V, 100mA driving capability, Ivcca=200uA @ Idrive=0, Pulse Width Modulator, UMC 65nm SP/HVT Logic Low-K process.

7409
USB 1.1.OTG PHY IP, OTG, UMC 65nm SP process

USB 1.1 On-The-Go PHY, UMC 65nm SP/HVT Logic Low-K process.

7410
Voltage Detector IP, 4 Levels, UMC 65nm LL process

4-Level Voltage Detector for USB-OTG, UMC 65nm LL Logic/RVT Low-K process and 2.5V overdrive 3.3V device.

7411
D/A Converter IP, 18 bits, Audio Codec, UMC 90nm SP process

18-Bit MONO Sigma-Delta Digital-to-Analog converter Codec with speaker driver, UMC 90nm SP/RVT Low-K Logic process.

7412
RC Oscillator IP, Output: 10MHz, UMC 90nm LL process

Internal-RC, trimmable fixed frequency 10MHz. Input 1.08V-1.32V VBG=0.5V, UMC 90nm LL Logic/RVT Low-K process.

7413
DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 90nm SP process

Boosting voltage from 3.3V to 5V, 100mA driving capability, Ivcca=200uA @ Idrive=0mA, Pulse Width Modulator, UMC 90nm SP/RVT Low-K process.

7414
USB 1.1.OTG PHY IP, OTG, UMC 90nm SP process

USB 1.1 OTG PHY, UMC 90nm SP/RVT Low-K Logic process.

7415
Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm LL process

UMC 90nm LL/RVT Logic process synchronous high density Single Port SRAM memory compiler with redundancy feature.

7416
Timer IP, Real Time Clock, Clock cource: 100MHz APB bus or 32768Hz input, Soft IP

Faraday's Real Time Clock is a flexible, low area, and Low Power real time clock.

7417
General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 90nm SP process

UMC 90nm SP/RVT process Multi-Voltage Generic IO CELL USING 3.3V GOX52 IO.

7418
Specialty PCI IO IP, 5V tolerance, UMC 0.18um G2 process

UMC 0.18um GII Logic process 5.0V tolerant PCI 33/66 IO cells.

7419
General Purpose IO IP, UMC 90nm LL process

UMC 90nm LL Logic/RVT process true 1.2/3.3V standard IO Cell Library (3.3V Analog IO).

7420
RSA Public Key Cryptography Exponentiation Accelerator

The modular exponentiation accelerator IPX-RSA is an efficient arithmetic coprocessor for the RSA public-key cryptosystem. It performs the Ae mod M calculation and therefore offloads the most ...

7421
DDR3 SDRAM Controller

Supports industry standard Double Data Rate (DDR2 and DDR3) SDRAM. ; Pipeline access allows continuous data bursting and hidden command execution. ; Page hit detection supports fast column ...

7422
3GPP LTE 3GPP2 1xEV-DO Turbo Decoder with Ping Pong Input and Output Memories

This is a fully compatible 3GPPTM LTE and 3GPP2 1xEV-DO Release B turbo decoder with ping-pong input and output memories. The PCD03V offers unparalleled performance, low complexity and features ...

7423
Pipelined FFT

The Pipelined FFT IP Core provides efficient continuous data FFT calculations at the rate of one point per clock cycle. Used in both FPGA and ASIC devices, and excellent for applications ...

7424
Parallel Butterfly FFT

Parallel butterfly structure for multiple point (rank-at-a-time) processing performance. The Parallel Butterfly FFT IP Core provides efficient continuous data FFT calculations at the rate ...

7425
Full HD/UHD video and vision integrated platform solution

The full HD/UHD video and vision platform integrates both full-HD/UHD multi-standard video codecs and embedded vision acceleration on a single silicon footprint with minimum load on the host ...

7426
DVB Common Scrambling Algorithm (CSA) cores

The Helion DVB-CSA cores implement the ETSI specified Common Scrambling Algorithm (CSA) which is used to provide content protection and conditional access support for MPEG video streams within ...

7427
AHB to APB Mailbox Interface

CoreMBX (Mail Box) allows data messages (mail) to pass back and forth from one processing element to another. The user is able to choose whether this message passing capability is implemented ...

7428
Reed Solomon Decoder

CoreRSDEC is an RTL generator that produces an Microsemi FPGA–optimized Reed-Solomon (RS) decoder core based on user-defined parameters. RS codes are a class of error-correcting codes used ...

7429
LCD Host LVDS Interface, Dual Pixel 20-112Mhz (SVGA/QXGA)

V-Trans 's LVDS Display interface IP is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital display data between a display source ...

7430
Audio PLL - Fractional-N ±0.05 ppm accuracy

This PLL can generate all the frequencies used by audio systems from a stable clock of 10 to 40Mhz. Audio clock is 256*fs0 or 384*fs1, where fs0 is 192kHz or 176.4kHz and fs1 is 96kHz or 88.2Khz. ...

7431
PLL general purpose / DDR memory, 50-500Mhz, 4 phases (0/90/180/270)

The VT18PLL500 is a macro cell for clock generation. The output frequency is adjustable from 50 to 500MHz. It is a fully integrated PLL based clock generator with a phase frequency detector ...

7432
Triple Video DAC 10-Bits, 240Mhz

This IP is composed of a triple channel 10-bits 240 MS/s DAC, designed for industry standard 0.18um 1P6M CMOS technology supplied at 3.3V. Each independent DAC uses a segmented current steering ...

7433
Triple DAC 10-Bits, voltage output - 10Mhz, 3.3V/1.3V full-scale

This IP is a triple channel 10-bits 10 MS/s general purpose voltage output DAC, optimized for analog LCD controller application and designed for industry standard 0.18um 1P6M CMOS technology ...

7434
Crystal oscillator 10-30Mhz with digital frequency adjustment ± 100ppm

The V-Trans VT18DCXO crystal oscillator cell provides a low phase-noise output, with a low frequency variation over temperature. Oscillation frequency can be digitally adjusted ( +/- 100ppm) ...

7435
Triple HD-video AFE digitizer - 10bits/170Mhz - 8bits/205Mhz

This macro is a triple-channel, 8/10-bits video analog front end (AFE) that incorporates all of the functions required to digitize High Definition YpbPr/YUV (component) video signals and RGB ...

7436
GPON ONT SERDES (90nm UMC)

PSI2488-U9 is a GPON ONT SERDES capable of receiving serial data at the rate of 2.488Gbps and transmitting data at the rate of 1.244Gbps. The transmitter serializes 8 bit parallel data to a ...

7437
Low-Power Bandgap Reference Circuit - UMC 0.09um

High precision Bandgap Reference Circuit with very low Power consumption of less than 10µA

7438
M-JPEG Encoder (100 embedded quality levels)

This IP core has been developed to be a complete standards compliant High Speed M-JPEG Hardware Encoder. It has been implemented on several ASIC and FPGA targets.

7439
ADC 12-bit 80Mhz Dual channel - 3.3V

This dual channel Analog -to-Digital converter IP is based on a monolithic differential pipelined architecture with output error correction logic providing 12 bits conversion accuracy up to ...

7440

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