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LVDS IP Listing

504 IP Cores (81 - 120)

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LVDS TX PHY & Controller

Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connected to a terminated receiver through a constant-impedance ...

81
666 Mbps LVDS Transceiver IP

The MXL-TXRX-LVDS is a LVDS transceiver implemented in digital CMOS technology. It supports up to 666 Mbps. It is compatible with IEEE Std 1596, EIA-644-A, and OIF-SFI4 specifications. Each ...

82
1.25 Gbps Four-Channel (4CH) LVDS Serializer with Pre-emphasis

The MXL-LVDS-TX-4CH is a high performance 4-channel LVDS Transmitter implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel ...

3 Testimonials
Joseph Hong, General Manager, Faraday Technology Corporation

83
1.25 Gbps 4-Channel LVDS Deserializer in Samsung 28FDSOI

The 4-Channel LVDS Deserializer is a high performance 4-channel LVDS Receiver implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. ...

4 Testimonials
Joseph Hong, General Manager, Faraday Technology Corporation

84
LVDS Rx IO IP, UMC 0.18um G2 process

0.13um LVDS RX IO PAD, UMC 0.13um HS/HVT-FSG process.

85
LVDS Rx IO IP, UMC 90nm SP process

0.18UM RX (PAD), UMC 0.18um GII Logic process.

86
LVDS Transmitter IP, Tx IO, UMC 55nm SP process

0.18um TX PAD, UMC 0.18um Logic RVT-FSG process.

87
LVDS Receiver IP, 20MHz - 135MHz , UMC 0.18um G2 process

DLL-based LVDS RX, VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation frequency, UMC 0.13um HS FSG Logic process.

88
LVDS Transmitter IP, 8MHz - 135MHz , UMC 0.13um HS/FSG process

8M~135MHz DLL-based LVDS TX, UMC 0.13um HS/FSG process.

89
LVDS Tx IO IP, UMC 90nm SP process

LVDS TX Pad, UMC 0.35um Logic process.

90
LVDS Transmitter IP, 700Mbps, UMC 90nm SP process

2.5V LVDS Transmitter 700Mbps, UMC 55nm SP Low-K Logic process.

91
LVDS Receiver IP, UMC 90nm SP process

DLL-based LVDS RX, UMC 55nm SP/RVT Low-K Logic process.

92
LVDS Transmitter IP, 16MHz - 178MHz, UMC 55nm SP process

2.5V LVDS Transmitter 16~178MHz, UMC 55nm SP/RVT Low-K Logic process.

93
LVDS Rx IO IP, 500Mbps, UMC 90nm LL process

Low Power LVDS Receiver IO 500Mbps, UMC 55nm SP/RVT Low-K Logic process.

94
LVDS Rx IO IP, UMC 0.18um Logic process

LVDS RX IO, UMC 90nm SP/RVT Low-K Logic process.

95
LVDS Transmitter IP, 8MHz - 135MHz, 4 channels, UMC 0.13um SP/FSG process

2.5V 4 channel LVDS Transmitter 8~135MHz, UMC 90nm SP/RVT Low-K process.

96
LVDS Receiver IP, 8MHz - 135MHz, UMC 0.13um SP/FSG process

2.5V LVDS Receiver 8~135MHz, UMC 90nm SP process.

97
LVDS Receiver IP, 700Mbps, UMC 0.13um SP/FSG process

Low Power LVDS Receiver 700Mbps, UMC 90nm SP/RVT Low-K Logic process.

98
LVDS Transmitter IP, 8MHz - 135MHz, UMC 90nm SP process

2.5V LVDS Transmitter 8~135MHz, UMC 90nm SP process.

99
LVDS Receiver (Vcc=3.3V,Vcore=2.5V, Freq=800Mbps, Vin=200mV)

0.25um CMOS technology (Chartered Semiconductor) ; 800Mbps switching speed ; Low power dissipation ; IEEE 1596.3 SCI LVDS standard compliance ; ANSI/TIA/EIA-644 LVDS standard compliance ; 3.3V/2.5V ...

100
LVDS Transmitter (Vcc=3.3V,Vcore=2.5V, Freq=800Mbps, Vout=350mV)

0.25um CMOS technology (Chartered Semiconductor) ; 800Mbps switching speed ; Low power dissipation ; IEEE 1596.3 SCI LVDS standard compliance ; ANSI/TIA/EIA-644 LVDS standard compliance ; 3.3V/2.5V ...

101
LVDS Receiver (Vcc=3.3V,Vcore=1.8V, Freq=800Mbps,Vin=200mV, Short Specification)

0.18um CMOS technology ; 800Mbps switching speed ; Low power dissipation ; IEEE 1596.3 SCI LVDS standard compliance ; ANSI/TIA/EIA-644 LVDS standard compliance ; 3.3V/1.8V dual power supply ; ...

102
LVDS Receiver (Vcc=3.3V,Vcore=1.8V, Freq=800Mbps,Vin=200mV, Long Specification)

Using the 0.18um CMOS technology ; Meets or exceeds the requirements of ANSI TIA/EIA-644 Standard ; Operate with dual power (3.3V / 1.8V) ; Low power dissipation 20mW at 400MHz ; Typical differential ...

103
LVDS Transmitter (Vcc=3.3V,Vcore=1.8V, Freq=800Mbps,Vout=350mV)

Using the 0.18um CMOS technology ; Meets or exceeds the requirements of ANSI TIA/EIA-644 Standard ; Operate with dual power (3.3V / 1.8V) ; Low power dissipation 25mW at 400MHz ; Low voltage ...

104
LVDS Receiver (Vcc=3.3V,Vcore=1.2V, Freq=1Gbps,Vin=200mV)

0.13um CMOS technology (Chartered Semiconductor) ; 800Mbps switching speed ; Low power dissipation ; IEEE 1596.3 SCI LVDS standard compliance ; ANSI/TIA/EIA-644 LVDS standard compliance ; 3.3V/1.2V ...

105
LVDS Transmitter (Vcc=3.3V,Vcore=1.2V, Freq=800Mbps,Vout=350mV)

0.13um CMOS technology (Chartered Semiconductor) ; 800Mbps switching speed ; Low power dissipation ; IEEE 1596.3 SCI LVDS standard compliance ; ANSI/TIA/EIA-644 LVDS standard compliance ; 3.3V/1.2V ...

106
LVDS Specialty IO - IBM 45 nm SOI12S0

ARM offers a broad portfolio of silicon-proven Interface IP designed to meet varying system architectures and standards required for today's SoC. The broad array of General Purpose I/O, and ...

107
Video LVDS SerDes Transmitter-Receiver IP Core

The Video LVDS SerDes Transmitter / Receiver IP Core provides a complete, easy-to-use Serializer/Deserializer (SerDes) solution to interface a wide variety of video host systems to Flat Panel ...

108
LVDS Transmitter 1250Mb/s, 800Mhz clock with RSDS support

V-Trans 's LVDS technology solutions eliminate the trade-offs in speed, low power, low noise (EMI), and BOM cost saving for high performance data transmission applications. This LVDS transmitter ...

109
LVDS Receiver 1250Mb/s, 800Mhz clock

V-Trans 's LVDS technology solutions eliminate the trade-offs in speed, low power, low noise (EMI), and BOM cost saving for high performance data transmission applications. This LVDS receiver ...

110
LVDS serdes 28:4 channel compression TX 20-170Mhz

LVDS serdes 28:4 channel compression TX 140-1190 Mbs x4 FPD-LINK Transmitter 24-bit color 20-170Mhz This FPD Link Transmitter Macro is based on National Semiconductor openLDI specification ...

111
LVDS serdes 4:28 channel decompression RX 8-150Mhz

FPD-LINK 24-bit color, 8-150Mhz Receiver LVDS serdes 4:28 channel decompression RX 56-1050 Mbs x4 V-Trans 's FPD Link Receiver Macro is based on National Semiconductor openLDI specification ...

112
LCD Host LVDS Interface, Dual Pixel 20-112Mhz (SVGA/QXGA)

V-Trans 's LVDS Display interface IP is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital display data between a display source ...

113
FPD-link, 30Bits Color LVDS Receiver, 150Mhz (SVGA/WXGA)

Now available up to 150Mhz (90Mhz previously) V-Trans 's FPD Link Receiver Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer ...

114
LVDS Receiver - 931Mbps

931Mbps

115
LVDS Transmitter - 931Mbps, support low swing

931Mbps, support low swing

116
LVDS Specialty I/O - TSMC 40 nm CLN40G

ARM offers a broad portfolio of silicon-proven Interface IP designed to meet varying system architectures and standards required for today's SoC. The broad array of General Purpose I/O, and ...

117
LVDS Specialty IO - IBM 45 nm SOI12S0

ARM offers a broad portfolio of silicon-proven Interface IP designed to meet varying system architectures and standards required for today's SoC. The broad array of General Purpose I/O, and ...

118
LVDS Specialty I/O - Tower 130 nm TS13SL

ARM offers a broad portfolio of silicon-proven Interface IP designed to meet varying system architectures and standards required for today's SoC. The broad array of General Purpose I/O, and ...

119
Dual FPD-link Transmitter, 30/24-bits color, 40-170 Mhz (SVGA/HDTV@120hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression

This FPD-Link Transmitter Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital display data between a display source and ...

120

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