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Analog pll and minipll IP Listing

574 IP Cores (81 - 120)

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CC-100IP-RF Analog and RF Sensitivity Enhancement IP

The CC-100IP-RF is a RF and Analog Frontend Sensitivity Enhancement IP Block that embeds a Hyper-Capacitor with a Capacitance Multiplication, Series Inductance Nullification, Cybersecurity Enhancement ...

Generis Spice Model for the CC-100IP-RF IP

81
Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks

nLR-Charny-ref-[1.62-3.63]-[0.8-2.5]-Ixx.02, as any Power Management Virtual Component designed by Dolphin Design, is readily retargetable toward any submicron CMOS process.

82
Linear Regulator, Low-noise optimized for sensitive application such as RF or PLL blocks

-

83
GLOBALFOUNDRIES 22nm FDSOI 1.8v/0.8v PLL

This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 800MHz to 3200MHz. By setting DM [5:0] and DN [10:0] to different values according ...

84
Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks

nLR-Charny-ref-[1.62-3.63]-[0.8-2.5]-Ixx.02, as any Power Management Virtual Component designed by Dolphin Design, is readily retargetable toward any submicron CMOS process.

85
Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks

Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks

86
Input 25~66MHz, output 200~800MHz wide range SSCG PLL, UMC 28nm HPC/RVT process.

Input 25~66MHz, output 200~800MHz wide range SSCG PLL, UMC 28nm HPC/RVT process.

87
Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process.

Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process.

88
Input 1M-200M Hz, output 12M-300MHz, frequency synthesizable PLL; UMC 0.13um CMOS image sensor process

Input 1M-200M Hz, output 12M-300MHz, frequency synthesizable PLL; UMC 0.13um CMOS image sensor process

89
Input 2M-200M Hz, output 12M-300MHz, frequency synthesizable PLL; UMC 0.13um CMOS image sensor process

Input 2M-200M Hz, output 12M-300MHz, frequency synthesizable PLL; UMC 0.13um CMOS image sensor process

90
Input 10M-310M Hz, output 20M-310M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT Process

Input 10M-310M Hz, output 20M-310M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT Process

91
Input 10-200MHz, output 25-400MHz, frequency synthesizable PLL; UMC 0.11um EFLASH logic process

Input 10-200MHz, output 25-400MHz, frequency synthesizable PLL; UMC 0.11um EFLASH logic process

92
Input 372M ~ 540MHz, output 5M ~ 197MHz, PLL; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

Input 372M ~ 540MHz, output 5M ~ 197MHz, PLL; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

93
The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz according to the user setting. UMC 0.11um AE process.

The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz according to the user setting. UMC 0.11um AE process.

94
Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 65nm Logic LL/RVT Low-k process

Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 65nm Logic LL/RVT Low-k process

95
Input 20M-50M Hz, output 300M-600M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT process

Input 20M-50M Hz, output 300M-600M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT process

96
Input 12MHz, output 900 MHz/1200MHz, 600 MHz/800 MHz, 360 MHz/480MHz, 300 MHz/400MHz, frequency synthesizable PLL; UMC 55nm SP/RVT LowK Logic Process

Input 12MHz, output 900 MHz/1200MHz, 600 MHz/800 MHz, 360 MHz/480MHz, 300 MHz/400MHz, frequency synthesizable PLL; UMC 55nm SP/RVT LowK Logic Process

97
Input 10M-50M Hz, output 25M-1.3G Hz, frequency synthesizable PLL; UMC 28nm HPC Process

Input 10M-50M Hz, output 25M-1.3G Hz, frequency synthesizable PLL; UMC 28nm HPC Process

98
Input 20M-200M Hz, output 1000M-1500M Hz, frequency synthesizable PLL; UMC 65nm LL-RVT Low-K process

Input 20M-200M Hz, output 1000M-1500M Hz, frequency synthesizable PLL; UMC 65nm LL-RVT Low-K process

99
Input 32.768KHz, Output 12 and 48MHz PLL; UMC 55nm LP/RVT Logic Process

Input 32.768KHz, Output 12 and 48MHz PLL; UMC 55nm LP/RVT Logic Process

100
Input 32.768KHz, Ouput 12 and 24MHz PLL, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

Input 32.768KHz, Ouput 12 and 24MHz PLL, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

101
Input 6~27MHz, output 160~3000MHz frequency synthesizable PLL; UMC 28HPC process

Input 6~27MHz, output 160~3000MHz frequency synthesizable PLL; UMC 28HPC process

102
Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH RVT LowK Logic Process

Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH RVT LowK Logic Process

103
Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process

Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process

104
Input 200MHz~400MHz, output 200MHz~1600MHz frequency synthesizable PLL; UMC 28nm HPC Logic Process

Input 200MHz~400MHz, output 200MHz~1600MHz frequency synthesizable PLL; UMC 28nm HPC Logic Process

105
Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process

Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process

106
Input 12M Hz, output 40M-850M Hz, frequency synthesizable PLL; UMC 28nm HPC Logic Process

Input 12M Hz, output 40M-850M Hz, frequency synthesizable PLL; UMC 28nm HPC Logic Process

107
Input 6~27MHz, Output 62.5~2000MHz PLL, UMC 28nm HPC process.

Input 6~27MHz, Output 62.5~2000MHz PLL, UMC 28nm HPC process.

108
Input 10M-200M Hz, output 20M-400M Hz, frequency synthesizable PLL; UMC 55nm LP/RVT Low-K Logic Process

Input 10M-200M Hz, output 20M-400M Hz, frequency synthesizable PLL; UMC 55nm LP/RVT Low-K Logic Process

109
This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL; UMC 40nm LP Logic Process

This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL; UMC 40nm LP Logic Process

110
MMWave 80GHz PLL with VCO frequency range 19.00-20.25 GHz

MMWave 80GHz Analog FracN PLL with VCO frequency range 19.00-20.25 GHz, Including Integrated PFD, CP, LPF, VCO

111
Bluetooth Low Energy (BLE) analog PHY

B55NLL_BLE_PMU PHY provides complete Bluetooth Low Energy (BLE) analog PHY. The RF is a high performance 2.4GHz ISM band wireless transceiver. It integrates both high sensitivity receivers and ...

112
Analog Front End: 16x 12-bit 200 MSPS ADCs, 14x Voltage DACs, 4x 250 MSPS DACs, 4x TVM, LDO

The ODT-AFE-8A1P-16FFCT is a highly integrated AFE designed in a 16nm CMOS process. The AFE includes eight 9-bit, 1GSPS ADCs, multiple LDOs and reference generators, and a 3rd party PLL IP. ...

113
Multi-protocol, Low Power Serdes - TSMC 28 CLN28HPL

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ...

114
PCI Express GEN-3/Display Port SERDES PHY - Samsung 28 28LPP

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ...

115
Programmable Low Power V-by-One SERDES - GLOBALFOUNDRIES 65 65G

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ...

116
PCI Express GEN-3/SATA3 SERDES PHY - Samsung 28 28FDSOI

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ...

117
PCI Express GEN 3/4 Port SERDES PHY - Samsung 14LPP

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ...

118
Low Power PCIe2/SATA3SERDES PHY - TSMC 28HPC

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ...

119
1-10G Low Power SERDES - TSMC 40G

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ...

120

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