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Low voltage IP Listing

2819 IP Cores (1121 - 1160)

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TSMC CLN5PLVT 5nm Clock Generator PLL - 300MHz-1500MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1121
TSMC CLN6FF 6nm Clock Generator PLL - 800MHz-4000MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1122
TSMC CLN6FF 6nm Clock Generator PLL - 400MHz-2000MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1123
TSMC CLN6FF 6nm Clock Generator PLL - 200MHz-1000MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1124
TSMC CLN6FFLVT 6nm Clock Generator PLL - 1200MHz-6000MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1125
TSMC CLN6FFLVT 6nm Clock Generator PLL - 600MHz-3000MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1126
TSMC CLN6FFLVT 6nm Clock Generator PLL - 300MHz-1500MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1127
UMC L110AELL 110nm Clock Generator PLL - 120MHz-600MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1128
UMC L110AELL 110nm Clock Generator PLL - 60MHz-300MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1129
UMC L110AELL 110nm Clock Generator PLL - 30MHz-150MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1130
UMC L28EHV 28nm Clock Generator PLL - 600MHz-3000MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1131
UMC L28EHV 28nm Clock Generator PLL - 300MHz-1500MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1132
UMC L28EHV 28nm Clock Generator PLL - 150MHz-750MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1133
UMC L28EHVLVT 28nm Clock Generator PLL - 900MHz-4500MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1134
UMC L28EHVLVT 28nm Clock Generator PLL - 450MHz-2250MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1135
UMC L28EHVLVT 28nm Clock Generator PLL - 225MHz-1125MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1136
UMC L28HPCLVT 28nm Clock Generator PLL - 880MHz-4400MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1137
UMC L28HPCLVT 28nm Clock Generator PLL - 440MHz-2200MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1138
UMC L28HPCLVT 28nm Clock Generator PLL - 220MHz-1100MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

1139
100MHz Fractional-N/SSC PLL

The ll_pll0521s01_ln05lpe_4007011 is a 1.8V/0.85V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis. It consists of a phase frequency detector ...

1140
UMC L180G 180nm DDR DLL - 56MHz-280MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

1141
UMC L180G 180nm DDR DLL - 42MHz-210MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

1142
UMC L150HS 150nm DDR DLL - 76MHz-380MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

1143
UMC L150HS 150nm DDR DLL - 57MHz-285MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

1144
UMC L130SP 130nm DDR DLL - 76MHz-380MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

1145
UMC L130SP 130nm DDR DLL - 57MHz-285MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

1146
UMC L130HS 130nm DDR DLL - 104MHz-520MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

1147
UMC L130HS 130nm DDR DLL - 78MHz-390MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

1148
TSMC CL018G 180nm DDR DLL - 56MHz-280MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

1149
TSMC CL018G 180nm DDR DLL - 42MHz-210MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

1150
TSMC CL018E 180nm DDR DLL - 76MHz-380MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

1151
TSMC CL018E 180nm DDR DLL - 57MHz-285MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

1152
TSMC CL015G 150nm DDR DLL - 76MHz-380MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

1153
TSMC CL015G 150nm DDR DLL - 57MHz-285MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

1154
TSMC CL015LV 150nm DDR DLL - 76MHz-380MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

1155
TSMC CL015LV 150nm DDR DLL - 57MHz-285MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

1156
2.5 Gbps Transceiver core

The MXL2500A is a full speed Gigabit transceiver implemented using a digital CMOS technology. It can be used for high-speed bi-directional point-to-point data transmission. The transmitter accepts ...

1157
4.25 Gbps Quad Multistandard SerDes

The MXL4254A is a Quad Gigabit SerDes implemented in digital CMOS technology. Each of the four channels supports data rate from 1 to 4.25 Gbps. It is compatible with router-backplane links, ...

1158
666 Mbps LVDS Transceiver IP

The MXL-TXRX-LVDS is a LVDS transceiver implemented in digital CMOS technology. It supports up to 666 Mbps. It is compatible with IEEE Std 1596, EIA-644-A, and OIF-SFI4 specifications. Each ...

1159
LVDS Transmitter (Vcc=3.3V,Vcore=1.8V, Freq=800Mbps,Vout=350mV)

Using the 0.18um CMOS technology ; Meets or exceeds the requirements of ANSI TIA/EIA-644 Standard ; Operate with dual power (3.3V / 1.8V) ; Low power dissipation 25mW at 400MHz ; Low voltage ...

1160

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