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Coloriage pat patrouille IP Listing

2270 IP Cores (1281 - 1320)

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UHS-II PHY for SD4/SD5 TSMC 16nm FF

SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely area and power efficient implementation. ...

1281
UHS-II PHY for SD4/SD5 TSMC 12nm FF

SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely area and power efficient implementation. ...

1282
Narrow band - IoT Ultra-Low power UE RF Transceiver IP

This is an ultra-low-power Cat-M/NB1 UE RF Transceiver IP solution optimized for IoT and M2M applications. The RF IP supports Release-17 frequency bands with Integrated Power Amp. The NB-IoT ...

1283
SMIC 28nm USB3.0 Dual Role PHY/Type-C

The USB3.0 Type-C PHY IP is designed to the USB 3.0, USB2.0 Specification and the USB Type-CTM USB Cable and Connector Specification Revision 1.1.

1284
7 track Extra Low Consumption standard cell library with Dual voltage capability (1.8 V +/-10% / 1.1 V +/- 10%)

TSMC 180 BCD, SESAME eLC DV is specifically designed to enable robust dual voltage operation, with characterizations taking into account physical phenomena linked to low voltage.

1285
7 track Extra Low Consumption standard cell library with Dual Voltage capability

TSMC 180 RFID, SESAME eLC is specifically designed to enable Dual Voltage operation (1.8 V +/- 10% 1.1 V +/- 10%) and to operate near threshold voltage at 0.6 V

1286
Secure Execution Processor

The Geon™ Secure Execution Processor is a low-power, 32-bit processor IP core with built-in protection of sensitive code and data. It uses two or more cryptographically separated execution ...

1287
AES-XTS for Storage Encrypt/Decrypt Core

The AES-XTS encryption IP core implements encryption/decryption for sector-based storage data. It uses the AES block cypher, in compliance with the NIST Advanced Encryption Standard, as a subroutine. ...

1288
USB BCK Technology (22nm, 40nm, 55nm, 110nm)

In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK function. M31’s patented BCK (Built-in-Clock, a.k.a. Crystal-less) technology ...

1289
RapidIO 2.0 PHY & Controller

The Innosilicon Serdes Combo PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interface for RapidIO. The PHY supports the RapidIO ...

1290
Intelligent Sensor and Power Management Design Platform

The IQonIC Works ISP is an integrated ASIC design platform for low power analog/mixed signal ASICs for IoT, Smart Home, Healthcare, Wearables, and Industrial applications that will simplify, ...

1291
AES IP Core

Encryption and Decryption are fed with an input of 128 bits length and an initial key of one of the supported key lengths (128, 192 and 256). The AES IP Core is fully verified against “The ...

1292
WiFi 802.11 b/g/n Transceiver 2.4GHz+PA+TR/Switch+Balun+onChip/Match

4th generation of SAberTek WiFi transciever IP, SBR75xxIoT, is a fully integrated 1x1 transceiver IPs for 2.4GHz 802.11bgn applications. It includes the receiver, transmitter, Frac-N frequency ...

1293
WiFi 802.11 b/g/n Transceiver 2.4GHz+PA+Balun+onChip/Match

4th generation of SAberTek WiFi transciever IP, SBR75xxIoT, is a fully integrated 1x1 transceiver IPs for 2.4GHz 802.11bgn applications. It includes the receiver, transmitter, Frac-N frequency ...

1294
ChipScope Pro (IBERT) for Virtex-6 GTH

The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-6 FPGA GTH transceivers is a customizable core that can be used to evaluate and monitor Virtex-6 ...

1295
In-System IBERT IP

The LogiCORE In-System IBERT IP enables 2D eye scans of Ultrascale™/Ultrascale+™ transceivers to be performed the in Vivado® Serial I/O Analyzer tool. It utilizes data from the user design ...

1296
UltraScale+ Device Integrated Block for PCI Express (PCIe)

The Xilinx® UltraScale+ FPGA Integrated Block for PCI Express® solution IP core is a high-bandwidth, scalable, and reliable serial interconnect building block solution for use with UltraScale+™ ...

1297
2.5Gbps Ethernet MAC IP Core

The 2.5GMAC IP core supports the ability to transmit and receive data between a host processor and an Ethernet network. The main function of the Ethernet MAC is to ensure that the Media Access ...

1298
2.5Gbps Ethernet PCS IP Core

The Lattice 2.5 Gbps Ethernet PCS IP core implements the state machine functions for the physical coding sublayer (PCS) described in the IEEE 802.3z (1000BaseX) specification. Note that the ...

1299
DDR3 PHY

The Lattice Double Data Rate (DDR3) Physical Interface (PHY) IP is a general-purpose IP that provides connectivity between a DDR3 memory Controller (MC) and the DDR3 memory devices compliant ...

1300
DDR3 SDRAM Controller

The Lattice Double Data Rate (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard DDR3 memory devices/modules ...

1301
Ethernet MAC Cores

The Ethernet Media Access Controller (MAC) core can be configured to operate in either the Gigabit mode (1000 Mbits/sec data rate) or the Fast Ethernet mode (10/100 Mbits/sec data rate). Netlist ...

1302
JESD207 IP

JESD207 is a Radio Front End – Base Band Digital Parallel (RBDP) interface between a Radio Front-end integrated circuit (RFIC) and a Baseband integrated circuit (BBIC). This IP core together ...

1303
Quad GbE Over SONET/SDH

Lattice's Quad GbE Over SONET/SDH Bridge is a hard IP Core implemented in two Lattice ORCA4E06 devices that act as a bridge between two Intel Dual-Port GbE MAC devices (part number IXF1002) ...

1304
RLDRAM Controller MACO Core

The Reduced Latency Dynamic Random Access Memory (RLDRAM) Controller is a general-purpose memory controller that interfaces with industry standard RLDRAM. The controller can be configured to ...

1305
SPI 4.2 MACO Core

The LatticeSCM SPI4 MACO™ IP core implements an industry standard SPI4.2 interface used to transfer both variable length packets and fixed cell sizes between PHY and Link Layer devices ...

1306
Video Frame Buffer

The Video Frame Buffer IP core buffers video data in external memory to be displayed on output devices such as computer monitors, projectors, etc. The Video Frame Buffer IP core supports image ...

1307
Viterbi Decoder

Lattice's Viterbi Decoder is a parameterizable IP core with an efficient algorithm for decoding different combinations of convolutionally-encoded sequences. (Convolutional encoding is a process ...

1308
UDP/IP Offload Engine (UOE)

UOE is high performance and highly customizable UDP/IP hardware stack compliant with RFC 768 (for UDP) and RFC 791 (for IPv4)/RFC 2460(for IPv6). As shown in the figure below, the UOE core ...

1309
Soft FIFO

CoreFIFO is a fully configurable Soft FIFO controller. It is designed to support SmartFusion2 and IGLOO2 device families. The core implements standard asynchronous FIFO and synchronous FIFO ...

1310
Ultra-Low Latency 1G Ethernet MAC and PCS

The Ultra-Low Latency 1G Ethernet MAC and PCS is the industry leading solution for latency critical Ethernet applications. The core is designed using advanced design techniques leading to unmatched ...

1311
40/100G Ethernet MAC and PCS + RS-FEC

The 40/100G Ethernet MAC & PCS + RS-FEC is a multi-rate IP core supporting 40G and 100G line rate. The core is designed using advanced design techniques leading to unmatched ultra-low gate count ...

1312
25G Ethernet MAC and PCS + RS-FEC

The 25G Ethernet MAC & PCS + RS-FEC is compliant with IEEE802.3by -2016 and 25/50G Ethernet Consortium specifications. The core is designed using advanced design techniques leading to unmatched ...

1313
LTE NB-IOT (NB1) power optimized transceiver for cellular IoT

Palma Ceia SemiDesign offers a low power, 3GPP Release 14 NB-IOT (LTE Cat NB1) transceiver. The transceiver IP is targeted for the Internet of Things (IoT) and Machine-to-Machine (M2M) applications. ...

1314
IEEE 1588 V2 Ordinary and Boundary Clock

PreciseTimeBasic is a IEEE1588-2008 V2 compliant clock synchronization IP core for Xilinx FPGAs. It is capable of accurately time stamp IEEE 1588 telegrams and also to provide a compatible timer. ...

1315
Arm Cortex-A7

The Cortex-A7 processor provides up to 20% more single thread performance than the Cortex-A5 and incorporates all features of the high-performance Cortex-A15 and Cortex-A17 processors, including ...

1316
Arm Cortex-A72

The Arm® Cortex®-A72 is an efficient high-performance processor that implements the Armv8-A architecture. The Cortex-A72 processor can be paired with the Cortex-A53 processor in a big.LITTLE ...

1317
Arm Cortex-A73

The Arm® Cortex®-A73 is the most-efficient high-performance processor that implements the Armv8-A architecture. The Cortex-A73 processor can be paired with the Cortex-A53 or Cortex-A35 processor ...

1318
Arm Cortex-R5

The Arm Cortex-R5 processor forms a simple migration path from the Cortex-R4 processor, and onwards to the higher performance Cortex-R8 and Cortex-R52 processors. The Cortex-R5 processor builds ...

1319
Power efficient, high-performance neural network hardware IP for automotive embedded solutions

Our IP Core enables you to create chips for automotive nn acceleration with excellent sustained performance and low power under real workloads The aiWare hardware IP Core is highly customizable ...

1320

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