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로아 배틀마스터 스킬 IP Listing

18542 IP Cores (13881 - 13920)

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CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process

CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process

13881
10bit 150MSPS 3-ch Video DAC,UMC 28nm HPC process

10bit 150MSPS 3-ch Video DAC,UMC 28nm HPC process

13882
10bit 250MSPS Current-steering Video D/A Converter; UMC 0.11um HS/FSG Logic Process

10bit 250MSPS Current-steering Video D/A Converter; UMC 0.11um HS/FSG Logic Process

13883
10bits 1MHz R-2R D/A Converter with rail to rail voltage output ; UMC 55nm eFlash (SST) process

10bits 1MHz R-2R D/A Converter with rail to rail voltage output ; UMC 55nm eFlash (SST) process

13884
10bits 1MHz R-2R D/A Converter with rail to rail voltage output ; UMC 55nm ULP process

10bits 1MHz R-2R D/A Converter with rail to rail voltage output ; UMC 55nm ULP process

13885
12bits 1MHz Voltage output R-2R D/A Converter; UMC 55nm SP-RVT process

12bits 1MHz Voltage output R-2R D/A Converter; UMC 55nm SP-RVT process

13886
12 bit 1MSPS R-2R DAC; UMC 55nm eFlash process

12 bit 1MSPS R-2R DAC; UMC 55nm eFlash process

13887
Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, UMC 40nm LP/RVT Logic Process.

Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, UMC 40nm LP/RVT Logic Process.

13888
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process

13889
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process

13890
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm LP/RVT LowK Logic Process

Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm LP/RVT LowK Logic Process

13891
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical version

Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical version

13892
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process

13893
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process

13894
DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS

DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS

13895
DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS

DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS

13896
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT LowK Logic Process

Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT LowK Logic Process

13897
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process

Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process

13898
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.

Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.

13899
MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process

MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process

13900
MIPI Transmitter 80~1500MHz combo with CMOS input using MIFS C40LP Logic Process

MIPI Transmitter 80~1500MHz combo with CMOS input using MIFS C40LP Logic Process

13901
8V ~ 25V HV driver, UMC 0.35um 3.3V/5V/40V CDMOS logic process

8V ~ 25V HV driver, UMC 0.35um 3.3V/5V/40V CDMOS logic process

13902
1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process

1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process

13903
55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type,

55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type,

13904
Self-contained ring oscillator, frequency 32KHz. VCC11A=1.08V~1.32V; UMC 55nm LP/RVT Low-K Logic process

Self-contained ring oscillator, frequency 32KHz. VCC11A=1.08V~1.32V; UMC 55nm LP/RVT Low-K Logic process

13905
Internal-R, frequency 48MHz/8MHz. Input 1.08V-1.32V; UMC 55nm EFLASH process

Internal-R, frequency 48MHz/8MHz. Input 1.08V-1.32V; UMC 55nm EFLASH process

13906
NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm EFLASH process. _x000D_

NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm EFLASH process.

13907
An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process

An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process

13908
1~50V/V low offset PGA for SAR-ADC ; UMC 0.18um Mixed-Mode PROCESS

1~50V/V low offset PGA for SAR-ADC ; UMC 0.18um Mixed-Mode PROCESS

13909
Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH/EE2PROM ULP RVT LowK Logic Process

Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH/EE2PROM ULP RVT LowK Logic Process

13910
Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL using MIFS C40LP Logic Process

Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL using MIFS C40LP Logic Process

13911
Input 2MHz~16MHz, output 16~1000MHz, 1.08~1.32V small-size PLL; UMC 55nm Eflash Process.

Input 2MHz~16MHz, output 16~1000MHz, 1.08~1.32V small-size PLL; UMC 55nm Eflash Process.

13912
Power Management Unit(5-sets DC-DC, 2-sets REG, PowerSwitch, and Li-ion Charger) for Audio Platform; UMC 0.35um 3.3V/5V CDMOS process

Power Management Unit(5-sets DC-DC, 2-sets REG, PowerSwitch, and Li-ion Charger) for Audio Platform; UMC 0.35um 3.3V/5V CDMOS process

13913
Input VCC18V=1.8V, 1.8V Power On Reset for East-West Orientation; UMC 28nm HPC Logic Process

Input VCC18V=1.8V, 1.8V Power On Reset for East-West Orientation; UMC 28nm HPC Logic Process

13914
Input VCC18V=1.8V, 1.8V Power On Reset for North-South Orientation; UMC 28nm HPC Logic Process

Input VCC18V=1.8V, 1.8V Power On Reset for North-South Orientation; UMC 28nm HPC Logic Process

13915
Vrr=1.96V Vfr=1.76V, input 3.3V, Core Type; Power On Reset; UMC 0.35um Logic process

Vrr=1.96V Vfr=1.76V, input 3.3V, Core Type; Power On Reset; UMC 0.35um Logic process

13916
Vrr=1.45V Vfr=1.35V, input 1.8V, Core type; Power On Reset; UMC 0.18um Logic GII process_x000D_

Vrr=1.45V Vfr=1.35V, input 1.8V, Core type; Power On Reset; UMC 0.18um Logic GII process

13917
Vrr=0.8V,Vfr=0.65V,input VCC=1.2V, 1.2V Power On Reset; UMC 55nm e-flash Logic Process

Vrr=0.8V,Vfr=0.65V,input VCC=1.2V, 1.2V Power On Reset; UMC 55nm e-flash Logic Process

13918
Input VCC=0.9V, 0.9V Power On Reset without Vfr; UMC 28nm HPC Logic Process

Input VCC=0.9V, 0.9V Power On Reset without Vfr; UMC 28nm HPC Logic Process

13919
Vrr=0.63V,Vfr=0.56V,input VCC=0.9V, 0.9V Power On Reset; UMC 28nm HPC Logic Process

Vrr=0.63V,Vfr=0.56V,input VCC=0.9V, 0.9V Power On Reset; UMC 28nm HPC Logic Process

13920

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