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Ryzen 7 9800X3D IP Listing

2499 IP Cores (1561 - 1600)

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MIPI D-PHY/LVDS Combo TX (Transmitter) for Automotive in Samsung 28FDSOI

The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY and a high performance ...

1561
SMIC 0.16um Low Leakage 9T Standard Cell Library

SMIC 0.16um Low Leakage 7T High-Density Standard Cell Library

1562
This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution.

This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution. The ADC includes internal sample/hold circuits, a capacitive DAC, ...

1563
GLOBALFOUNDRIES 65nm LVDS Transmitter

The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link transmission between Host and Flat Panel Display ...

1564
ST28nm LVDS Transmitter

The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link transmission between Host and Flat Panel Display ...

1565
6 track Ultra High Density standard cell library at TSMC 90 nm with dual voltage capability

TSMC 90 uLL, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest alternative to flip-flops).

1566
6 track Ultra High Density standard cell library at TSMC 90 nm with dual voltage capability

TSMC 90 LPeF, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest alternative to flip-flops).

1567
6 track Ultra High Density standard cell library at TSMC 55 nm

Foundry Sponsored, TSMC 55 LeFP, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest alternative to flip-flops). ...

1568
14-bit, 50 MSPS Ultra Low Power ADC in 28nm CMOS

The ODT-ADP-14B50M-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process, implemented using Omni Design's groundbreaking low power SWIFT technology. This 14-bit ...

1569
14-bit, 300 MSPS Ultra Low Power ADC in 28nm CMOS

The ODT-ADP-14B300M-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process, implemented using Omni Design's groundbreaking low power SWIFT technology. This 14-bit ...

1570
14-bit, 600 MSPS Ultra Low Power ADC in 28nm CMOS

The ODT-ADP-14B600M-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process, implemented using Omni Design's groundbreaking low power SWIFT technology. This 14-bit ...

1571
14-bit, 1200 MSPS Ultra Low Power ADC in 28nm CMOS

The ODT-ADP-14B1P2G-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process, implemented using Omni Design's groundbreaking low power SWIFT technology. This 14-bit ...

1572
Advanced 2D Graphics Contoller

BADGE works as a graphics engine in embedded systems, but doesn’t suffer from the short life cycles affecting the usual graphics controllers. It is very flexible. Can interface to numerous ...

1573
25G LL MAC /PCS Ethernet IP for FPGA

The Chevin Technology 25G LL MAC/PCS combines the 25G MAC and 25G PCS IP cores to obtain the lowest possible latency while simplifying the integration of 25Gbit/s Ethernet connectivity in Xilinx ...

1574
POR

Static current is low to 700nA； Typical POR delay time is about 1.9ms；0.0143mm2

1575
2K128 MTP

XRX013HVPLFLASH_2K128 is a HV compatible embedded non-volatile memory IP with 2K128 ROM density. This IP could be used for code storage, firmware update, parameter setting, trimming and calibration, ...

1576
3K128 MTP

XRX013HVPLFLASH_3K128 is a HV compatible embedded non-volatile memory IP with 3K128 ROM density. This IP could be used for code storage, firmware update, parameter setting, trimming and calibration, ...

1577
10 Bit 40 MS/s Pipeline ADC

The IP consists of a 10 bit 40 MS/s pipeline ADC. A time-interleaved architecture with 1.5 bit per stage is used. The operational amplifiers are shared between the interleaved stages for reduced ...

1578
PAD - HHGrace 110nm ULL

Ultra-low size DUP-PAD total solution; Standard I/O size is low to 72um*40um; HBM ESD: ±2000V; MM: ±200V; CDM: ±500V; LU: 150mA

1579
12-bit 140 MSPS IQ DAC

The 12-bit 140 MSPS IQ DAC employs a high-performance current steering architecture and provides optional differential current output or differential voltage output. The bandgap and current ...

1580
SATA 2 HOST ON CYCLONE 5 GX

The LDS SATA 2 HOST_C5GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a ALTERA Cyclone V GX FPGA. The LDS SATA 2 HOST_C5GX IP is compliant with ...

1581
SATA 3 HOST IP on ARRIA 10 FPGA

The LDS-SATA3-HOST-A10GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a INTEL ARRIA 10 GX FPGA. The LDS-SATA3-HOST-A10GX IP is compliant with ...

1582
Smart Grid PLC Baseband Processor

The ntG3_BBP is a fully compliant ITU-T G.9903 baseband modem that can be used in a wide range of smart grid applications over power lines, including smart metering and energy management in ...

1583
SRC-Pro : 24-bit -130dB THD+N Multi-Channel Audio Asynchronous Sample Rate Converter

The ASRC-pro (CWda52) is part of Coreworks family of multi-channel Asynchronous Audio Sample Rate Converters (ASRC). This core can be used to interface digital audio equipments operating at ...

1584
4-to-1 RF Multiplexer

TI-RF-MUX is a 4-to-1 RF multiplexer designed with an internal current feedback output amplifier which gain can be adjusted externally. There is a possibility of optional usage of two 4-to-1 ...

1585
Embedded FPGA

Speedcore eFPGA IP brings the power and flexibility of programmable logic to ASICs and SoCs. Customers specify their logic, RAM, MLP and DSP resource needs, then Achronix configures the Speedcore ...

1586
E31 Balanced performance and efficiency RISC V core

The SiFive E31 Standard Core is the world's most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient ...

1587
10G Low latency, 32-bit MAC + PCS @ 312.5MHz Solution (32-bit and 64-bit UI)

The 10Gbps 32-bit Ethernet IP solution offers a fully integrated IEEE802.3-2015 compliant package for NIC (Network Interface Card) and Ethernet switching applications. This extremely low latency ...

1588
802.11ah ULP Wifi Radio

imec’s ULPWIFI Radio is a pre-standard design for the upcoming IEEE 802.11ah standard (draft D5.0) and supports the mandatory 1MHz and 2MHz channel modes, optimized for low power as well as ...

1589
40nm low-power wide area SoC radio TSMC CMOS

Imec offers a white-box IP license with support on a multi-standard ultra-low power (ULP) 780-930MHz radio transceiver SoC. The analog frond end targets the following standards: IEEE 802.15.4g-SUN, ...

1590
Ultra-Low Power Fractional-N digital PLL for IoT Applications in 40nm CMOS

IMEC’s divider-less All-Digital Phase Locked Loop (ADPLL) combines world’s lowest power consumption with state-of-the-art performance and small silicon area. The ADPLL supports industrial ...

1591
40G/50G Ethernet Subsystem

The Xilinx® LogiCORE™ IP 40G/50G Ethernet solution provides a 40 Gigabit or 50 Gigabit per second (Gbps) Ethernet Media Access Controller integrated with a PCS/PMA in BASE-R/KR modes or a ...

1592
MIPI CSI Controller Subsystems

The Xilinx MIPI CSI2 Receiver Subsystem and MIPI CSI 2 Transmitter Subsystems implement the Mobile Industry Processor Interface (MIPI) based Camera Serial Interface (CSI-2) according to version ...

1593
UltraScale / UltraScale+ Interlaken

The Xilinx® LogiCORE™ IP UltraScale™ architecture integrated IP core for Interlaken is a scalable chip-to-chip interconnect protocol designed to enable the following for use in select UltraScale ...

1594
Zynq-7000 Processing System IP

Xilinx provides the Processing System IP Wrapper for the Zynq®-7000 to accelerate your design and its configuration for your embedded products The Processing System IP is the software ...

1595
CSIX to PI40

As stated by the CSIX Forum, the CSIX standard defines the physical and message layers of the interconnect between traffic managers (TM) and the switching fabric. The CSIX interface is designed ...

1596
DDR SDRAM Controller - Non-Pipelined

This version of the Lattice DDR SDRAM Controller does not have pipelining, and is significantly smaller than the pipelined version. DDR (Double Data Rate) SDRAM was introduced as a replacement ...

1597
DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4

DDR (Double Data Rate) SDRAM was introduced as a replacement for SDRAM memory running at bus speeds over 75MHz. DDR SDRAM is similar in function to the regular SDRAM but doubles the bandwidth ...

1598
DDR/DDR2 SDRAM Controller MACO Core

The DDR/DDR2 Synchronous Dynamic Random Access Memory (SDRAM) Controller MACO Core is a general-purpose memory controller that interfaces with industry standard DDR/DDR2 SDRAM devices and modules. ...

1599
DDR3 PHY

The Lattice Double Data Rate (DDR3) Physical Interface (PHY) IP is a general-purpose IP that provides connectivity between a DDR3 memory Controller (MC) and the DDR3 memory devices compliant ...

1600

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