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Sd IP Listing

809 IP Cores (161 - 200)

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eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FF PLUS

Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core voltage of 1.1V and I/O voltage of 1.8/3.3V ...

161
(SDR) Software Defined Radio for high end 4G/ 5G and large MIMO application

This SDR is a development platform for realization networks like 4G/5G and other radio applications involving more than 4 or 8 antenna ports. The SDR platforms have the mix of practical deployment ...

162
SD 5.1 / eMMC 5.1 Host Controller IP

Our Host IP is specially designed to combo both SD eMMC features. SD feature: The Secure Digital (SD) Card, supports SD5.1 and later specifications, ( A1, Video Speed Class Performance ) ...

163
SD4.1 UHS- II PHY IP

SD4.1 UHS-II IP utilizes distinctive SerDes technology to attain a speed of 312MB/s for UHS-II while maintaining low power consumption. This PHY IP is versatile, suitable for use on both the ...

164
1st Generation Software Defined Radio RF IP

This is the 1st Generation SDR RF IP that supports 1x2 and support the frequency ranging from 300MHz to 2.8 GHz with a support of up to 40MHz Bandwidth. the SDR Gen.1 supports the ADC/DAC with ...

165
2nd Generation Software Defined Radio RF IP

This is the 2nd Generation SDR RF IP that supports 2x2 and support the frequency ranging from 100MHz to 3.8 GHz with a support of up to 120MHz Bandwidth. the SDR Gen.2 supports the ADC/DAC with ...

166
ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)

ONFI PHY block is used to either transmit signal and data to NAND Flash interface, or receive the data from NAND Flash by Flash controller IP. MDLL sets the delay time for the control signal ...

167
Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 40nm Logic Process.

Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 40nm Logic Process.

168
Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process.

Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode ...

169
DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process

DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process

170
UMC 28nm Logic and Mixed-Mode HPC Processs Multi-Voltage BOAC SD3.0 I/O Cell library

UMC 28nm Logic and Mixed-Mode HPC Processs Multi-Voltage BOAC SD3.0 I/O Cell library

171
UMC 0.11um AE/HS logic process Multi-Voltage BOAC SD3.0 I/O Cell library

UMC 0.11um AE/HS logic process Multi-Voltage BOAC SD3.0 I/O Cell library

172
SD host controller wih ahb interface, compliant with the SD Host Controller Standard Specification Version 2.00

SD host controller wih ahb interface, compliant with the SD Host Controller Standard Specification Version 2.00

173
SDI Mapper for TICO-RDD35 & TicoXS (JPEGXS) lightweight codecs

Extend 4K or 8K using today's deployed HD-SDI/3G-SDI systems The IPX-SDI-MAP IP-cores enable to efficiently transport TICO RDD35 and TicoXS (JPEG-XS) over existing SDI. It enables to ...

174
Integrated ESD cell designs for General I/O, eMMC I/Os, SDIOs, and ONFI I/O(12nm~180nm)

M31’s I/O Libraries now include integrated ESD cell designs for General I/O, eMMC I/Os, SDIOs, and ONFI I/O. We provide standard JEDEC ESD level and customized high-level ESD I/O across various ...

175
Special I/O-eMMC/SDIO (22nm, 28nm, and 40nm)

SD (Secureity Digital) and eMMC (embedded MultiMedia Card) I/Os are non-volatile memory interface technologiesy with high bandwidth capabilities, which is particularlymainly developed for flash ...

176
eMMC 5.1 /SD-SDIO3.0 Host Controller & PHY

Dolphin Technology delivers custom, synthesizable IP to support specific design requirements. The DTI EMMC controller provides the logic to integrate a Host and PHY controller supporting embedded ...

177
SD4.0 / UHS-II Host Controller & PHY

Compliant with the following specifications: - Part 1 Physical Layer Specification Version 5.0 - Part 1 UHS-II Addendum Version 1.02 - Part A2 SD Host Controller Specification Version 4.20

178
SDRAM DDR4/3/2 Host Controller & PHY

Dolphin Technology offers high performance DDR4/3/2 SDRAM and LPDDR4/3/2 SDRAM Memory Controller IP across a broad range of process technologies. These Memory Controllers are fully compliant ...

179
SDRAM LPDDR5/4x/4/3/2 Host Controller & PHY

Dolphin Technology offers high performance DDR4/3/2 SDRAM and LPDDR4/3/2 SDRAM Memory Controller IP across a broad range of process technologies. These Memory Controllers are fully compliant ...

180
SDIO Device IP

SDIO DEVICE interface provides full support for the SDIO DEVICE synchronous serial interface, compatible with SD specification part E1 SDIO 4.10. Through its compatibility, it provides a simple ...

181
SDIO Host IP

SDIO HOST interface provides full support for the SDIO HOST CONTROLLER synchronous serial interface, compatible with SDIO version 4.10 specification. Through its compatibility, it provides ...

182
SMPTE SDI Receiver IP

SMPTE SDI Receiver is full-featured, easy-to-use, synthesizable design,compatible with SMPTE ST 425 specification. Through its SMPTE SDI Receiver compatibility, it provides a simple interface ...

183
SMPTE SDI Transmitter IP

SMPTE SDI Transmitter is full-featured, easy-to-use, synthesizable design,compatible with SMPTE ST 425 specification. Through its SMPTE SDI Transmitter compatibility, it provides a simple interface ...

184
SDI to Video Bridges

The LogiCORE™ IP SDI Tx and RX Video Bridge cores are designed to interface the SDI ports of the SMPTE SDI core to the video ports of the AXI4-Stream core. The input of the SDI Rx Video Bridge ...

185
SMPTE SDI

Supports emerging standards for lowering cost of uncompressed HD video transport Reduce the cost of multichannel SD/HD/3G-SDI designs through integration of SMPTE compliant SDI ...

186

75dB CT SD ADC & 10-bit DAC

187

DDR SDRAM Controller - Non-Pipelined

This version of the Lattice DDR SDRAM Controller does not have pipelining, and is significantly smaller than the pipelined version. DDR (Double Data Rate) SDRAM was introduced as a replacement ...

188

DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4

DDR (Double Data Rate) SDRAM was introduced as a replacement for SDRAM memory running at bus speeds over 75MHz. DDR SDRAM is similar in function to the regular SDRAM but doubles the bandwidth ...

189

DDR/DDR2 SDRAM Controller MACO Core

The DDR/DDR2 Synchronous Dynamic Random Access Memory (SDRAM) Controller MACO Core is a general-purpose memory controller that interfaces with industry standard DDR/DDR2 SDRAM devices and modules. ...

190

DDR3 SDRAM Controller

The Lattice Double Data Rate (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard DDR3 memory devices/modules ...

191

DDR3 SDRAM Controller IP Core Pinout Utility

Overview The DDR3 Pinout Generation Utility is a GUI tool that is capable of generating the pinout and preference files that contain information for a design that uses the DDR3 SDRAM ...

192

LPDDR SDRAM Controller

The LPDDR Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard LPDDR memory devices/modules compliant with ...

193

LPDDR3 SDRAM Controller

A Lattice FPGA based LPDDR3 solution – The Lattice Low Power Double Data Rate (LPDDR3) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller ...

194

Quad GbE Over SONET/SDH

Lattice's Quad GbE Over SONET/SDH Bridge is a hard IP Core implemented in two Lattice ORCA4E06 devices that act as a bridge between two Intel Dual-Port GbE MAC devices (part number IXF1002) ...

195

Soft SDRAM Controller for AXI Interface

CoreSDR_AXI is intended to provide a 64-bit advanced microcontroller bus architecture (AMBA®) advanced extensible interface (AXI) to an external single data rate (SDR) synchronous dynamic random ...

196

High-Performance Single Data Rate SDRAM Controller

CoreSDR_AHB provides a high performance interface to single data rate(SDR) synchronous dynamic random access memory(SDRAM) devices. CoreSDR_AHB accepts read and write commands using the AHB ...

197

High performance interface for SD/MMC memory cards

CoreMMC provides a MultiMedia Card (MMC) controller to interface with external MMC flash cards and eMMC devices. The CoreMMC controller allows you to store theboot images and boot the processor ...

198

SD/SDIO Device IP Core

SD/SDIO Combo Device IP core is an SD memory controller and an SDIO controller with an AHB interface. Combining with the optional our SD/SDIO Combo Device IP provides an integrated SD memory ...

199

DO-254 SDRAM Controller

The SDRAM Controller implements a controller for Single Data Rate Syncrhonous Dynamic Random Access Memory (SDR SDRAM) decives as specified in the JEDEC Standard No. 21-C Page 3.11.5.1 Release ...

200

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