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히토미 번역 IP Listing

18464 IP Cores (16961 - 17000)

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MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 16 FFC

In order to use the least amount of power and money, several production nodes use C-PHY/D-PHY Combo. The Combo PHY can be set up by users in either D-PHY or C-PHY mode to support a variety of ...

16961
MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 22 ULP

C-PHY/D-PHY Combo in numerous process nodes at low cost and power. To accommodate a range of applications, users can set this Combo PHY in either D-PHY or C-PHY mode. It also conforms to the ...

16962
MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 22 ULP

In order to use the least amount of power and money, several production nodes use C-PHY/D-PHY Combo. The Combo PHY can be set up by users in either D-PHY or C-PHY mode to support a variety of ...

16963
MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 28 HPC+

C-PHY/D-PHY Combo at low cost and power in several manufacturing nodes. Users have the option of setting this Combo PHY in either D-PHY or C-PHY mode to support a variety of applications. Additionally, ...

16964
MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 28 HPC+

Several production nodes employ C-PHY/D-PHY Combo to consume the least amount of energy and funds. Users can configure the Combo PHY in D-PHY or C-PHY mode to support a range of applications. ...

16965
MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 40 LP

C-PHY/D-PHY Combo in various production nodes at low cost and power. To accommodate a range of applications, users can set this Combo PHY in either D-PHY or C-PHY mode. It complies with the ...

16966
MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 40 LP

Many production nodes use the C-PHY/D-PHY Combo because it uses the fewest resources and energy. Users can configure the Combo PHY in D-PHY or C-PHY mode to support a range of applications. ...

16967
MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 40 LP

The MIPI M-PHY Gear 4 IP is compatible with the most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal ...

16968
MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 55 ULP

The most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification are ...

16969
MIPI C-PHY/D-PHY Combo CSI-2 TX 3.5Gsps/trio in TSMC 28nm

The MXL-CDPHY-3p5G-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5 and C-PHY v2.0. The ...

16970
Low-Power Deeply Embedded RISC-V Processor

The BA53 is a configurable, low-power, deeply-embedded RISC-V processor IP core. It implements a single-issue, in-order, 5-stage execution pipeline, and supports the RISC-V 32-bit base integer ...

1 Testimonial
Hugh O’Keeffe, CEO, Ashling

16971
Manchester Encoder / Decoder

The MAN_CODEC IP Core is a versatile encoder and decoder pair that converts a basic NRZ bitstream into a standard Manchester code and vice-versa. The encoder and decoder are provided as separate ...

16972
DDR5 Registering Clock Driver (RCD) (DDR5RCD01)

The DDR5RCD01 is a registering clock driver used on DDR5 RDIMMs and LRDIMMs. Its primary function is to buffer the Command/Address (CA) bus, chip selects, and clock between the host controller ...

16973
USB 2.0 PHY

The USB 2.0 PHY is a complete mixed-signal IP solution designed to implement OTG connectivity in a System-on-Chip (SoC) design targeted to a specific fabrication process using core and 2.5-V ...

16974
USB 3.0 PHY

The USB 3.0 PHY is a complete, mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into USB 3.0 SuperSpeed applications. The USB 3.0 PHY, usb3_sspxN_hspxN, ...

16975
MIPI D-PHY Bidir 2/4L

The MIPI D-PHY Bidirectional 2-Lane(4-Lane) macro implements the physical layer of bidirectional universal lanes for the MIPI D-PHY interface. The MIPI D-PHY Bidir 2/4L is stacked in a configuration ...

16976
MIPI D-PHY RX 2/4L

The MIPI D-PHY RX 2/4 Lanes macro implements the physical layer of universal lanes for the MIPI D-PHY interface, stacked in a two/four data lanes and one clock lane configuration. The MIPI D-PHY ...

16977
PCIe Gen1 PHY

The PCIe1 PHY is a complete mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into computer applications. The PCIe1 PHY pcie1_pipe_1xN includes ...

16978
PCIe Gen2 PHY

The PCIe2 PHY is a complete mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into PCI Express applications. The PCIe 2 PHY pcie2_pipe_PxL_xN ...

16979
SATA 6G PHY

The SATA 6G PHY is a complete mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into SATA 6G applications. The SATA 6G PHY sata6g_pma_xN includes ...

16980
XAUI PHY

The XAUI PHY is a complete mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into XAUI applications. The XAUI PHY dwc_xaui3g_xN_pma_xN includes ...

16981
DDR3/2 PHY

The DDR3/2 PHY is a complete mixed-signal IP solution designed to provide DDR 3/2 SDRAM connectivity in a System-On-a-Chip (SOC) design targeted to a specific fabrication process. The DDR3/2 ...

16982
DDR multi PHY

The DDR multiPHYs are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR2, DDR3, LPDDR2, LPDDR3 SDRAM memories up to 1066 Mbps data rates and Mobile ...

16983
DDR4 PHY

The DDR4 multiPHY is a complete mixed-signal IP solution designed to provide LPDDR3/LPDDR2/DDR3/DDR3U/DDR3L/DDR4 SDRAM connectivity in a System-On-a-Chip (SOC) design targeted to a specific ...

16984
HDMI 14 RX PHY

The HDMI Rx PHY is the physical layer of an HDMI receiver. The HDMI Rx PHY implements the analog front-end (AFE) of an HDMI receiver, the sampling and deserialization of the three data streams, ...

16985
HDMI 14 TX PHY

The HDMI Tx PHY is the physical layer of a single-link HDMI transmitter interface. The HDMI Tx PHY comprises three-line drivers for data transmission and an additional line driver for clock ...

16986
VDAC

This IP is composed of a single to sextuple channel 10-bit, 300MHz DAC designed for 40nm CMOS technology supplied at 3.3V. Each independent DAC uses a segmented current steering architecture, ...

16987
SAR ADC

16988
Pipeline ADC

16989
PLL

16990
All self-developed domestic IPs

VeriSyno offers network IP solutions tailored for the high-end server market. Our offerings predominantly focus on implementing 10G/1G data link layer and physical coding sublayer functions. ...

16991
High Speed PSRAM Solution

Our PSRAM solutions cover a range from 400Mbps to 1066Mbps, offering both normal-speed PSRAM digital IP and high-speed PSRAM mixed-signal IP. These solutions find wide applications in smart ...

16992
LDO

16993
POR

16994
M’ary Quadrature Amplitude Modulator IP in VHDL, FPGA and SDR

We present an implementation of Quadrature Amplitude Modulation (QAM) signal modulators using Field Programmable Gate Array (FPGA). The modulator is targeted at the low-level "RTL based" ...

16995
HBM3 PHY and Controller.

MSquare's HBM3 IP (the 3rd generation of High-Bandwidth Memory) is specifically tailored for applications that require high memory throughput and low latency, complying with the JESD238 memory ...

16996
ISO/IEC 21122-1 JPEG-XS Standard Codec

Jointwave X16 is a JPEG XS Codec (Encoder + Decoder) designed for visually lossless, real time video transmission/storage. X16 is compliant with the ISO/IEC 21122 standard for both FPGA and ...

16997
2.4GHz ISM Band ADPLL

The Orca Systems™ ORC9010 is a synthesized or synthesizable low-power all-digital phase-locked loop (ADPLL) Digital IP designed for 2.4GHz ISM band IoT applications such as Bluetooth and satellite ...

16998
High performance, extremely low latency and highly configurable ternary content-addressable memory IP

tCAM-IP is a high performance, extremely low latency and highly configurable ternary content-addressable memory IP. tCAM-IP can make deterministic search at 200MSPS continuously speed with constant ...

16999
ONFI 5.0 PHY IP

MSquare offers a silicon-proven ONFI 5.0 PHY IP that supports all modes of the Open NAND Flash Interface (ONFI) 5.0 specification. ONFI is an interface that connects external flash particles ...

17000

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