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Prism verilog IP Listing

834 IP Cores (241 - 280)

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MACsec Engine, 1G to 25G, Full Duplex, Integrated

As part of Rambus' award-winning silicon Intellectual Property (IP) product portfolio, the EIP-165 is a high-performance, split ingress/egress in-line MACsec frame engine that provides hardware ...

241
ZUC Crypto Accelerator

The EIP-48 is an efficient hardware implementation of the ZUC algorithm. Besides the basic ZUC stream cipher, the EIP-48 fully implements the 3GPP Confidentiality and Integrity algorithms 128-EEA3 ...

242
HDCP Engine

The EIP-116 High-bandwidth Digital Content Protection Control Path module provides the required technology for implementing all the secure access, cryptographic computations and cipher engine ...

243
HDLC & SDLC Protocol Controller

The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols. It is based on the Intel 8XC152 Global Serial Channel ...

244
I2C Slave Controller with User Register Array / Memory / FIFO / AMBA Interface

The I2C Controller IP Core implements an I2C Slave Controller, with a user parameterized Register Array or Memory (i.e SRAM / FIFO) or any Peripheral connecting on an AHB / APB / AXI / Avalon ...

245
Hs-Mode I2C Controller - 3.4 Mbps, Master / Slave w/FIFO

The Hs-Mode I2C Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bus in Hs-Mode (3.4 Mbit/s) / Fast-Mode Plus (1 Mbit/s) / Fast-Mode ...

246
Hs-Mode I2C Controller - 3.4 Mbps, Master w/FIFO

The Hs-Mode I2C Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bus in Hs-Mode (3.4 Mbit/s) / Fast-Mode Plus (1 Mbit/s) / Fast-Mode ...

247
Hs-Mode I2C Controller - 3.4 Mbps, Slave w/FIFO

The Hs-Mode I2C Controller IP Core interfaces user Registers to an I2C Bus or Memory (SDRAM / SRAM / Flash / FIFO) or any Peripheral or CPU connecting through an internal AHB / APB / AXI / Avalon ...

248
AMBA Parameter Configurable Multi-Channel DMA Controller (typically 1 to 256)

The Multi-Channel DMA Controller supports 1 – 32 independent data block / packet / stream transfers. The Direct Memory Access (DMA) Controller IP Core contains 1 - 32 DMA Controller Engines ...

249
I2C Slave Controller - Low Power, Low Noise Config of User Registers

The DB-I2C-S-SCL-CLK is an I2C Slave Controller IP Core focused on low power, low noise ASIC / ASSP designs requiring the configuration & control of registers with no free running clock. The ...

250
SPI Master / Slave Controller w/FIFO (APB Bus)

The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface ...

251
SPI Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)

The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface ...

252
SPI Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)

The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface ...

253
Display Controller - LCD / OLED Panels (AHB-Lite Bus)

The Digital Blocks DB9000AHB-Lite TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 3.0 AHB-Lite Bus V1.0 to a TFT LCD panel. In an FPGA, ASIC, or ASSP ...

254
MACsec 10G/25G

Comcores MACsec IP provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE. It protects components in Ethernet networks ...

255
SATA PHY

The SATA PHY is suitable for both Host and Device applications within a Serial ATA system. The SATA PHY operates to the Serial ATA specification using either a 10-bit or 20-bit interface to ...

256
True Random and Pseudorandom Number Generator

The true random generator core implements true random number generation. The core passes the American NIST Special Publication 800-22 and Diehard Random Tests Suites. It is compliant with FIPS ...

257
Ultra-Compact 3GPP Cipher Core

The ZUC1 core implements ZUC stream cipher in compliance with the 3GPP Confidentiality and Integrity Algorithms 128-EEA3 & 128-EIA3 version 1.6. It produces the keystream that consists of 32-bit ...

258
SSL/TLS Processor IP Core with an AXI Bus Interface

The SSL1 core implements SSL and/or TLS frameworks with a configurable variety of cipher suites. SSL1-AXI has a “lookaside” interface to the rest of system through two AXI interfaces: ...

259
HDCP 2.0 Encryption Suite

HDCP Suite consists of hardware and software components implementing the HDCP 2.0 protocol. The hardware components are fully synchronous and available as Verilog source. The software components ...

260
Generic CCM AES Core

The CCM1 cores are tuned for mid-performance generic AES-CCM applications per NIST SP 800-38C. Specific protocol implementations are available in integrated cores: - WPA2 for IEEE 802.11i ...

261
Generic CCM AES Core with CMAC Option

The CCM2 cores are tuned for mid-performance generic AES-CCM applications per NIST SP 800-38C. CCM2 core uses flow-trough design with dedicated inputs for key and nonce. Cores contain ...

262
ES-GCM/CCM/CCM*/EAX' Core

The GCE1-MP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard and encryption/authentication modes GCM, CCM, CCM*, and EAX’. It processes ...

263
Stallable Pipeline Register

The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built. The interface is fully compatible with a Standard FIFO interface and ...

264
Stallable Nto1 Contraction Pipeline Register

The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built. A parameter defines the ratio of the input width to the output width. ...

265
AXI Protocol Checker

The AXI Protocol Checker core is designed to monitor AXI interfaces. When attached to an interface, it actively checks for protocol violations and provides an indication of which violation occurred. ...

266
AXI4-Stream Protocol Checker

The AXI4-Stream Protocol Checker core monitors AXI4-Stream interfaces for protocol violations and provides an indication of which violation occurred. The checks are synthesizable versions ...

267
100-Gbps Ethernet MAC & PHY

Altera offers the 40 Gbps Ethernet (40GbE) and 100 Gbps Ethernet (100GbE) MegaCore® function intellectual property (IP) cores for building systems with very high throughput-rate standard Ethernet ...

268
40-Gbps Ethernet MAC & PHY

Altera offers the 40 Gbps Ethernet (40GbE) and 100 Gbps Ethernet (100GbE) MegaCore® function intellectual property (IP) cores for building systems with very high throughput-rate standard Ethernet ...

269
FIR Compiler II

The Altera® FIR Compiler II MegaCore function generates finite impulse response (FIR) filters customized for Altera devices. You can use the IP Toolbench interface to implement a variety of ...

270
LPDDR2 SDRAM Controller

The High-Performance Memory Controller II SDRAM MegaCore® function for Quartus® II design software v11.0 handles the complex aspects of using DDR, DDR2, and DDR3 SDRAM at speeds up to 933 ...

271
DO-254 AXI 7-Series DDRx (Limited) 1.00a

Maps AXI4 transactions coming from the MicroBlaze™ to the User Interface Block providing an industry-standard bus protocol interface to the memory controller. It enables the MicroBlaze™ ...

272
DO-254 Block Memory Generator 1.00a

Automates the creation of resource and power optimized block memories for Xilinx® FPGAs Note: Used as sub-IP within FIFO Generator

273
DO-254 Soft Error Mitigation

The Soft Error Mitigation (SEM) IP core performs SEU detection, correction, and classification. The core utilizes device primitives such as Virtex™-7 ICAP and ECC blocks to clock and observe ...

274
DO-254 AXI to PCI Bridge 1.00a

Provides full bridge functionality between the Xilinx® AXI interface and a 32-bit Revision 2.2 compliant Peripheral Component Interconnect (PCI™) bus.

275
Mosquito/Block Noise Reducer

The Mosquito/Block Noise Reducer effectively reduces mosquito and block noise associated with low bit-rate sources while resulting in minimal loss of spatial resolution.

276
SC7 Power Management Kit - CSMC 130 nm CSMC13G

ARM® Logic IP solutions are the ideal choice for advanced, deep submicron SoC designs. The Standard Cell Libraries are complemented by Power Management Kit and ECO Kit extensions, delivering ...

277
SC7 Power Management Kit - GLOBALFOUNDRIES 110 nm CH011N

ARM® Logic IP solutions are the ideal choice for advanced, deep submicron SoC designs. The Standard Cell Libraries are complemented by Power Management Kit and ECO Kit extensions, delivering ...

278
SC7 Power Management Kit - GLOBALFOUNDRIES 130 nm 130bcdlite

ARM® Logic IP solutions are the ideal choice for advanced, deep submicron SoC designs. The Standard Cell Libraries are complemented by Power Management Kit and ECO Kit extensions, delivering ...

279
SC12MC Power Management Kit - GLOBALFOUNDRIES 28 nm CMOS28HPP

ARM® Logic IP solutions are the ideal choice for advanced, deep submicron SoC designs. The Standard Cell Libraries are complemented by Power Management Kit and ECO Kit extensions, delivering ...

280

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