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Mueblerias en calama IP Listing

6470 IP Cores (361 - 400)

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Bluetooth Low Energy (BLE) RF IP

The VeriSilicon Bluetooth Low Energy (BLE) RF IP is a 2.4GHz ISM band transceiver which is designed for Bluetooth Smart or IEEE 802.15.4 based applications. It is compliant with the BLE 4.2 ...

361
Video Encoder Processor IP

Hantro VC9000E enables 8K encoding with a small silicon and high video quality single-core solution, or multi-core solution up to 8K@120fps, supporting AV1, HEVC, H.264, VP9 video formats and ...

362
Video Encoder Processor IP

Hantro VC9000NanoE is a multi-format video encoder supporting H.264, VP8 and JPEG, and it also supports VP8 for Google’s WebM and WebRTC with super lower power consumption.

363
VeriSilicon Bluetooth Low Energy (BLE) RF IP

Bluetooth Low Energy (BLE) RF IP provides a transceiver designed for Bluetooth Smart applications. It is compliant with the BLE specification (part of Bluetooth 5.2, volume- 6) and supports ...

364
Bluetooth Low Energy (BLE) RF IP

Bluetooth Low Energy (BLE) RF IP provides a transceiver designed for Bluetooth Smart applications. It is compliant with the BLE specification (part of Bluetooth 5.2, volume- 6) and supports ...

365
High Number of Streams Encoder For Data Center

Hantro VC9800E enables up to 256 streams encoding with high video quality single-core solution, or multi-core solution, supporting AV1, HEVC, H.264, VP9 video formats and JPEG. VeriSilicon's ...

366
nQrux® Confidential Computing Engine (CCE)

nQrux® Confidential Computing Engine (CCE) offers customisable solutions protecting data, code execution, and AI (Artificial Intelligence) models in distributed environments, such as cloud ...

367
CCSDS SCCC Turbo Encoder and Decoder

The recommended CCSDS 131.2-B-1 standard introduces a Serial Concatenated Convolutional Code (SCCC). Main goal of this code is to allow an efficient use of available bandwidth, by allowing to ...

368
CCSDS 231.0 LDPC Encoder and Decoder

The CCSDS 231.0 LDPC IP supports the LDPC coding schemes as defined by the CCSDS standard. The LDPC codes with rate 1/2, coded block lengths 128 and 512 are specially designed for telecommand ...

369
Flexible LDPC encoder/decoder

TC5100 is a highly flexible LDPC encoder/decoder Core. It can essentially cover all possible quasi-cyclic LDPC codes: WiFi, WiMAX, proprietary codes, and also 3GPP Next Release (5G NR) candidate ...

370
BLE5.2 RFIP in TSMC 55nm~22nm

ACTT’s Bluetooth Low Energy 5.2 Radio IP available from 55nm~22nm logic process node. The radio supports 1Mbps, 2Mbps and Long Range mode, which is fully compliant with Bluetooth® Low Energy ...

371
BLE5.2 RFIP in SMIC 55nm~22nm

ACTT’s Bluetooth Low Energy 5.2 Radio IP available from 55nm~22nm logic process node. The radio supports 1Mbps, 2Mbps and Long Range mode, which is fully compliant with Bluetooth® Low Energy ...

372
BLE & BT 5.2 dual mode RFIP in TSMC 55nm~22nm

ACTT’s Bluetooth 5.2 Radio IP available in 55nm~22nm logic process node. The radio supports BDR/EDR/BLE, which is fully compliant with Bluetooth® Low Energy Version 5.2. The IP core works ...

373
BLE & BT 5.2 dual mode RFIP in UMC 55nm~22nm

ACTT’s Bluetooth 5.2 Radio IP available in 55nm~22nm logic process node. The radio supports BDR/EDR/BLE, which is fully compliant with Bluetooth® Low Energy Version 5.2. The IP core works ...

374
Reed Solomon Forward Error Correction Encoder Decoder

Comcores RS FEC IP Core is a versatile solution for robust error correction in a wide range of applications, such as wireless communication, data storage, digital broadcasting, and beyond. Comcores ...

375
15.5nA Current Bias with Enable - Ultra Low Voltage (0.9V), Ultra Low Power (50nW) Silterra 0.18 μm

This macro-cell is an ultra low power general purpose current bias generator core designed for SilTerra 0.18µm CL180G CMOS technology. The circuit generates 7 × NMOS 15.5nA current branches ...

376
17nA Current Bias with Enable - Low Voltage (1.0V), Ultra Low Power (90nW @ 1.8V) TowerJazz 0.18 μm

This macro-cell is a low power general purpose current bias generator core designed for TowerJazz 0.18µm TS18SL CMOS technology. The circuit generates 2 × NMOS 17nA current branches. The ...

377
RSA public key cryptography with APB interface

The standard RSA module is available as an APB peripheral, where it seamlessly integrates with EnSilica's cryptography library. The peripheral can be configured for between 512 and 4096-bit ...

1 Testimonial
Afshin Rezayee, Founder and Co-President, Kili Corporation

378
RLS Adaptive Filter

The QR-Decomposition Least Squares Lattice (QRD-LSL) core is a high throughput IP core that finds application in challenging adaptive filtering. It computes the Recursive Least Squares solution ...

379
DES/TDES core

The eSi-DES block performs encryption and decryption of 64-bit words using the DES (Data Encryption Standard) and TDEA (Triple DES Encryption Algorithm) algorithm.

380
SHA256 & SHA224 core

The eSi-SHA256 core is an easy to use SHA hash accelerator peripheral for both SHA256 and SHA224. This is a cryptographic hash function designed by the United States National Security Agency ...

381
AGC Control and data plane core

The eSi-AGC core provides the control and data plane interfaces to an AGC module. The signal processing in the core consists of a sliding energy estimate and saturation detection.

382
Power and area optimised Bitcoin miner engine

The eSi-BTC core is a Bitcoin miner engine that perform double SHA256 Hash. It is design to deliver best in class silicon area and power for the next generation of low energy Bitcoin minder ...

383
Synchronous Ethernet (SyncE) ESMC and Enhanced ESMC core

NetTimeLogic’s Synchronous Ethernet (SyncE) Node is a full hardware (FPGA) only implementation of an ESMC frame Handler and State selector. The whole ESMC frame sending and receiving & decoding ...

384
14-stereo AAC-LC Audio Encoder

The IPB-AAC-LC-ME-14 is an IP core for encoding up to 14 stereo audio streams in real-time, in one of the following configurations: 14 stereo channels or 12 stereo channels and a 5.1 channel. ...

385
Video Timing Generator

Signal timing generator for high-resolution video and graphics applications. Module accepts RGB pixels and generates syncs, enable and blanking information. Supports direct connection to a wide ...

386
Video Test Pattern Generator

Pattern generator for video testing and prototyping. Wide range of test patterns in colour, greyscale and monochrome. Test patterns are configurable, allowing for different width bars, squares ...

387
SPI Master Serial Interface Controller

Master serial interface compatible with the popular SPI standard. Features a simple command interface and permits multiple SPI slaves to be controlled directly from your FPGA, CPLD or ASIC ...

388
UART Serial Interface Controller

UART compatible Serial Interface Controller with Receive and Transmit FIFOs and support for bit rates from 9600 to 921600 baud. UART is used extensively in test equipment and is the simplest ...

389
Precision Tone Decoder

Detects the presence of a single tone at a specified centre frequency. Features 16-bit data samples, programmable tone frequency, adjustable detection bandwidth and a high performance Digital ...

390
SPI Slave Serial Interface Controller

Slave serial interface compatible with the popular SPI standard. Permits an SPI Master to communicate with your FPGA, CPLD or ASIC device. The controller uses a series of registers as a data ...

391
ADS-B 978 MHz (UAT) Receiver

ADS-B (UAT) receiver offers a comprehensive solution for the reception of ADS-B Flight, Traffic and Weather information. Compatible with all FPGA and ASIC devices, the circuit has been design ...

392
Sony Camera LVDS Interface

The SONY_CAM_IF IP Core provides a simple way to connect the Sony® FCB-EV range of cameras to your FPGA. It serves as a direct replacement for an external LVDS receiver IC and takes advantage ...

393
Sine Function

Function y = sin(x) calculates the sine of an angle in radians. It has a high-speed, fully pipelined architecture and uses a polynomial with dynamic coefficients to calculate the result to within ...

394
SinCos Function

Function calculates the Sine and Cosine of input x in radians. Inputs are 18-bit signed values in the range -Pi to Pi. Output values are 17-bit signed in the range -1 to 1. Ideal for the ...

395
Packet-based Digital Radio Link

Fully custom Digital Radio Link based on either our FSK or PSK modulation schemes. Data is split into packets or frames and modulated for transmission over cable (e.g. coax/twisted pair) or ...

396
Front End Module operating from 24 – 30 GHz and can be used in low power Ka band applications

RFFEM01C Front End Module operates from 24 – 30 GHz and can be used in low power Ka band application. The input and output are matched to 50 ohms with on-chip DC blocking capacitors. The device ...

397
Front End Module operating from 2 – 7 GHz and can be used in S / C band for Wi-Fi 6 & SATCOM applications.

RFFEM02C Front End Module operates from 2 – 7 GHz and can be used in S / C for Wi-Fi 6 & SATCOM applications. The input and output are matched to 50 ohms with on-chip DC blocking capacitors. ...

398
Reed-Solomon Compiler, Encoder

The Reed-Solomon (RS) compiler offers a fully parameterizable RS coder and RS decoder. RS coder/decoders (CODECs) are widely used for error detection and correction in a wide range of digital ...

399
DES Encryption and Decryption Processor

The IP-ALDES core is the VHDL model of the processor, that performs DES encryption and decryption. The model is fully compliant with FIPS46-2.

400

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