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Silicon IP Catalog
Memory Controller & PHY
DDR
DDR PHY
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DDR PHY IP Core

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DDR PHY IP Listing

597 IP Cores (121 - 160)

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GDDR7 PHY & Controller

Innosilicon GDDR7 PHY is fully compliant to the JEDEC GDDR7 standard, supporting up to 32Gbps for PAM3 GDDR7. In pam3 mode, the byte consists of ten DQ and one DQE signals, the GDDR7 also supports ...

121
MCR DDR5 PHY

The INNOSILICON DDR Mixed-Signal MCR DDR5 PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible MCR DDR5 DIMM devices. It is optimized for low power ...

122
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process

Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process

123
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process

Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process

124
DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

125
DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

126
DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process

DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process

127
DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device

DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device

128
DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage ; UMC 65nm 1.0V with 2.5V Device SP/RVT LowK Logic Process

DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage ; UMC 65nm 1.0V with 2.5V Device SP/RVT LowK Logic Process

129
DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process

DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process

130
DDR2/MDDR Combo Command/Address Block ; UMC 0.13um HS/FSG Logic Process

DDR2/MDDR Combo Command/Address Block ; UMC 0.13um HS/FSG Logic Process

131
DDR2/DDR1/MDDR Combo Command/Address Block ; UMC 65nm LP/RVT LowK Logic Process

DDR2/DDR1/MDDR Combo Command/Address Block ; UMC 65nm LP/RVT LowK Logic Process

132
Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process

Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process

133
1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process

1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process

134
DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process

DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process

135
DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process

DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process

136
DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process

DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process

137
DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process

DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process

138
DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process

DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process

139
DDRII Data Block for Chip Application; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process

DDRII Data Block for Chip Application; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process

140
DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process

DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process

141
DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

142
DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process

DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process

143
DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device

DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device

144
DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process

DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process

145
DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process

DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process

146
Data block of 1:2 DDR2-PHY ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

Data block of 1:2 DDR2-PHY ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

147
1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process

1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process

148
DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process

DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process

149
DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process

DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process

150
DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process

DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process

151
DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process

DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process

152
DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process

DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process

153
DDRII Data Block for Chip Application; UMC 0.13um HS/FSG Logic Process

DDRII Data Block for Chip Application; UMC 0.13um HS/FSG Logic Process

154
DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process

DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process

155
DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process

DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process

156
DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process

DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process

157
DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device

DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device

158
DDR3/2 COMBO PHY CMD/ADDR BLOCK for 2 layer 8 bits DDR3 PCB ; UMC 40LP/RVT LowK Logic Process with 2.5V device

DDR3/2 COMBO PHY CMD/ADDR BLOCK for 2 layer 8 bits DDR3 PCB ; UMC 40LP/RVT LowK Logic Process with 2.5V device

159
Multi Protocol SERDES operating at up to 12.5Gbps (40nm TSMC)

PSI1250MP is a multi-protocol SERDES capable of operating at up to 12.5Gbps. PSI1250MP can provide interfaces for many applications operating from 9.5Gbps to 12.5Gbps. It also provides interfaces ...

160

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