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New Products

KiviCore
Post-Quantum Cryptography - Key Encapsulation IP Core (ML-KEM)
Arasan Chip Systems Inc.
eUSB 2.0 PHY IP
Certus Semiconductor
Radiation-Hardened GPIO, ODIO and LVDS Interface in SkyWater 90nm
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
VeriSilicon LTE Cat1.bis RF IP
FortifyIQ, Inc.
FortifyIQ High-Performance Hybrid Classical and Post-Quantum High-assurance (SCA/DPA/FIA resistant) Cryptography IP Core (ECC/RSA, ML-KEM, ML-DSA)

Blogs

ML-KEM explained: Quantum-safe Key Exchange for secure embedded Hardware
KiviCore
KiviCore
Accelerating System Design with Real-Time Simulation, Powered by AI Physics
Cadence Design Systems, Inc.
Cadence Design Systems, Inc.
Why What Where DIFI and the new version 1.3
Chip Interfaces ApS
Piotr Koziuk
Chip Interfaces ApS
How Edge AI is Transforming Medical Diagnostics
Key ASIC
Key ASIC
What Is A Foundry? The Hidden Hero Of Semiconductor Manufacturing
Rapidus Corporation
Accelerating Your Development: Simplify SoC I/O with a Single Multi-Protocol SerDes IP
Key ASIC
Key ASIC
Ceva Advancing Real-Time AI with Transformers and Intelligent Quantization
Ceva, Inc.
Roy Janco
Ceva, Inc.
A Guide to Building Chiplets Today While Shaping Tomorrow’s Standards
Arteris IP
Andy Nightingale
Arteris IP
How Simulation Is Advancing Quantum Computing R&D
Synopsys, Inc.
Igor Markov
Synopsys, Inc.
Next Steps for the Cadence and SkyWater MPW Service
Cadence Design Systems, Inc.
Cadence
Cadence Design Systems, Inc.
Automotive Ethernet with Comcores - Safety, Quality and ASIL certification of IP
Comcores
Comcores
Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum
Cadence Design Systems, Inc.
Cadence
Cadence Design Systems, Inc.

Articles

ST silicon photonics and BiCMOS technologies: the winning portfolio for AI optical interconnects
STMicroelectronics
STMicroelectronics
AI in VLSI Physical Design: Opportunities and Challenges
Japesh Kumar, Qualcomm
AI-Driven and Traditional Approaches to Accident Scenario Reconstruction
Vayavya Labs
Nitin Swamy
Vayavya Labs
From Theory to the Field: Why Side-Channel Protection Defines Post-Quantum Security
PQSecure Technologies
PQSecure Technologies
PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
Innosilicon Technology Ltd
Innosilicon Technology Ltd
Design Approaches and Architectures of RISC-V SoCs
Maven Silicon
Maven Silicon
Implementation of Metal ECO using Mask Programmable Cell for Hold Timing Violations
eInfochips, Inc.
Dhanyakumar Shah,Dharmik Lakhani
eInfochips, Inc.
Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware
Menta
Menta
Bridging Design Verification Gaps with Formal Verification
Karim Waseem, Si-vision
Post-Quantum Cryptography: Why Open Source alone is Not Enough for Secure IP Deployment
PQSecure Technologies
Dr. Reza Azarderakhsh
PQSecure Technologies
The Blind Spot of Semiconductor IP Sales
CoreHW
Petri Heliö, Principal IC Designer
CoreHW
SWE-Bench-C Evaluation Framework
Vayavya Labs
Vayavya Labs
Asic Technology
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FPGA and eFPGA Corner
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