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InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission ...
The next-generation UCIe physical layer IP, based on TSMC's N4 process, is expected to finalize its design later this year, supporting data transmission ... Read
The Creonic Doppler Channel IP core generates Doppler shift frequencies by precisely adjusting the phase of signal samples in real-time. Read
Chip Interfaces Successfully Completes Interlaken IP Interoperability Test with Cadence 112G ...
This milestone marks a significant achievement in ensuring seamless integration and reliable data transfer between the two technologies for applications ... Read
YorChip, Inc. and Chipcraft announce development of a low cost, low power 8 bit 200Ms/s ADC Chiplet. Currently no ultra-low power devices exist in open ... Read
BrainChip today announced the availability of its Akida™ advanced neural networking processor on the M.2 form factor, enabling a low-cost, high-speed ... Read
The National Aeronautics and Space Administration (NASA) awarded four contracts in 2024 to Alphacore to advance the development of cutting-edge microelectronics ... Read
Industry Expert Blogs
Cadence Blog Rajneesh Chauhan, Cadence
Ceva's Experts blog Amit Wix, Ceva
Quadric Blog Quadric
SemiWiki Daniel Nenni
Universal Chiplet Interconnect Express (UCIe) Controller
MIPI C-PHY/D-PHY Combo DSI RX+ IP (4.5Gsps/trio, 6.5Gbps/lane) ...
5.8GHz Fractional-N PLL synthesizer
PCIe 5.0 PHY for TSMC N3P
Multi-protocol wireless plaform integrating Bluetooth Dual Mode, ...
UCIe-S PHY, Standard Package
PCIe 6.2 Switch IP Controller
ONFI 4.0 NAND Flash PHY upto 800Mbps
8kx8 Bits OTP (One-Time Programmable) IP, X-FA- 0.18μm XH018 ...
RTP / UDP / IP Hardware Stack for H.264/H.265 NAL Video Streams ...
Flash Memory LDPC Decoder
5-60V Input Buck Regulator (Type-C EPR compatible)
VESA VDC-M Decoder
On-chip Security Enclave
WDT Verification IP
Simulation VIP for AMBA LTI
UCIe Verification IP
BoW Verification IP
MIPI D-PHY Rx IP, Silicon Proven in TSMC 22ULP
Industry Articles
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What is JESD204C? A quick glance at the standard
Chip Interfaces
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Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
Innosilicon
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Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Ram Niwas
eInfochips (An Arrow Company) -
Quantum Readiness Considerations for Suppliers and Manufacturers
Graeme Hickey
PQShield -
A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
AsicNorth
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Early Interactive Short Isolation for Faster SoC Verification
Ritu Walia
Siemens -
The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
PUF Security
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Advanced Packaging and Chiplets Can Be for Everyone
Boris Chau
Faraday Technology Corporation
