FPGAs aid in high-end memory interface design
![]() | |
EE Times: FPGAs aid in high-end memory interface design | |
Olivier Despaux (05/09/2005 10:00 AM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=162600285 | |
As designers of high-performance systems labor to achieve higher bandwidth while meeting critical timing margins, one performance bottleneck standing in their way is the memory interface. Double-data-rate SDRAMs and quad-data-rate SRAMs use source-synchronous interfaces through which data and clock (or strobe) are sent from the transmitter to the receiver. The clock is used within the receiver interface to latch the data. This eliminates interface control issues, such as the signal time of flight between the memory and the FPGA, but it raises fresh challenges that designers must address. One key issue is how to meet the various read-data capture requirements to implement a high-speed interface. As the data-valid window becomes shorter, it becomes more important, and at the same time more challenging, to align the received clock with the center of the data. ![]() The traditional method used by FPGA, ASIC and ASSP controller-based designs employs a phase-locked-loop or delay-locked-loop circuit that guarantees a fixed phase shift or delay between the source clock and the clock used for capturing data. The obvious drawback here is the delay is fixed to a single value and predetermined during the design phase. Thus, hard-to-predict variations within the actual system-caused by different trace routings to different memory devices, variations between FPGAs and system conditions such as process, voltage and temperature-can easily create skew whereby the predetermined phase shift is inaccurate. New silicon features, along with hardware-verified reference designs made available by the leading FPGA vendors, have overcome those challenges. Additionally, engineers must follow some basic rules to improve design cycle time. Do
Don't
Olivier Despaux (olivier.despaux@xilinx.com), product applications engineer at Xilinx Inc. (San Jose)
| |
- - | |
Related Articles
- Meeting signal integrity requirements in FPGAs with high-end memory interfaces
- Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 1)
- How to achieve timing-closure in high-end FPGAs
- The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes
- Achieving High Performance Non-Volatile Memory Access Through "Execute-In-Place" Feature
New Articles
- What tamper detection IP brings to SoC designs
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
Most Popular
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- A Heuristic Approach to Fix Design Rule Check (DRC) Violations in ASIC Designs @7nm FinFET Technology
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |