The best use of assertions in verification
![]() | |
EE Times: The best use of assertions in verification | |
Vinima Aggarwal (10/03/2005 10:00 AM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=171201900 | |
Hardware designers and verification engineers have embraced the use of assertions. They are a way to formally specify a design's intended behavior, which must hold true during the course of a design cycle. They provide an efficient way of improving overall design cycle productivity by cutting verification time. Now, engineers do not need to go back to simulation traces and logic blocks to identify the exact cause of error, as was true in the conventional verification process, where the design was verified after implementation. Assertions are written using formal semantics that can be verified for correctness through the use of software tools. Formal semantics make it possible to describe complex design properties in a simple and precise way and to detect hard-to-find and corner-case bugs. This reduces the designer's dependence on the use of simulation to check for functional correctness. The verification engineer creates assertions at the specification level, while the designer creates assertions at the architectural level. They can be written in SystemVerilog Assertions, if the design is written in SystemVerilog, or Property Specification Language for independent hardware description languages, such as VHDL or Verilog. Assertions are verified for correctness using both the simulation environment and formal environment, and design teams know they have written sufficient assertions when all points in the design specification are covered. Do
Don't
Vinima Aggarwal (vinima@verific.com), applications engineer at Verific Design Automation (Alameda, Calif.)
| |
- - | |
Related Articles
New Articles
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
Most Popular
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |