FPGA Soft Processor Design Considerations

This ever-shrinking development cycle also drives higher levels of efficiency and design flexibility. The combination of FPGA technology and soft processor cores has the potential to allow the integration of system design into a single FPGA device. This combination can provide previously unavailable design options. The technology evolution enables design teams to deal with their complex design challenges and rapid system development schedules.

Embedded FPGA Processor Definitions
Hardware Description Languages (HDLs) increase the range of options available to FPGA designers by enabling hardware implementation with the flexibility that language-based design provides. HDLs allow designers to implement flexible Intellectual Property (IP), often referred to as IP cores. IP is the implementation of reusable components, which describe and implement hardware functionality. IP cores are implemented via instantiation within the design to implement desired functionality, and can be implemented multiple times within a single design and within different design projects. Examples of common IP cores related to FPGA embedded processors include UARTs, Ethernet MAC, and processor units.

The three primary IP core categories include hard, firm, and soft cores. Hard IP cores involve the implementation of a silicon-level circuit within the FPGA fabric. Soft IP cores are design elements that can be implemented within the FPGA fabric. Soft cores are commonly implemented within an HDL language such as VHDL or Verilog. Firm IP cores are also design elements, which can be implemented within the FPGA fabric. Firm IP cores have a higher level of optimization and are often targeted for a specific device architecture or device. Firm cores are traditionally less portable than soft cores.

Firm IP cores traditionally have a mix of higher performance and more efficient resource utilization than do soft core implementations of the same functionality, given that they take advantage of specific device and architecture features. This article will not focus on the differences between firm and soft cores and will refer to firm and soft cores simply as soft cores. Some of the advantages of designing with soft IP cores include:

• Higher level of design reuse
• Reduced obsolescence risk
• Simplified design update or change
• Increased design implementation options through design modularization

All of the benefits and characteristics of soft IP cores are realized by soft processor cores implemented within FPGA components. A popular soft processor core example is Xilinx’s MicroBlaze processor core. This soft processor core is a 32-bit Reduced Instruction Set Computer (RISC) with the following characteristics:

• Harvard bus architecture
• Three-stage pipeline
• 32 general-purpose registers
• Two interrupt levels and exception handling capability
• Configurable cache
• Support for optional co-processing functionality
• Optional single precision floating-point unit (FPU) (IEEE-754 compatible)
• Standardized IBM Core Connect Bus interface

The MicroBlaze can operate at up to 200 MHz within a Virtex-4 (4VLX40-12) component. The range of resources required to implement a MicroBlaze soft processor is between 900 and 2,600 Xilinx Look-Up Tables (LUTs), depending on how the processor is configured. Design Selection Factors
Selecting a soft processor core can be a complex task with far-reaching design effects. Some of the most important FPGA soft processor core selection factors include:

• Cost of implementation
• Operational performance
• Power consumption
• Design and development tools
• Operating System considerations
• Debug options and capability
• Manufacturer collateral and technical support

The following sections address these design factors in more detail. Cost
The cost of a delivered design is typically the most important factor for the majority of embedded design projects. The delivered product cost is based on a combination of software and hardware development costs, material and manufacturing. There is a complex relationship between development costs and hardware costs. In the majority of embedded development projects software development and support costs exceed by a significant margin hardware-related costs. Some factors that affect this relationship include reuse, flexibility, and portability, resistance to obsolescence, development effort, schedule, and learning curves. Thus the cost of the processor element may not be the most significant design cost when considering the full product life cycle including derivative designs.

The first effort necessary to justify implementing a design with a soft FPGA processor core is completing a cost analysis that takes into account the potential benefits of FPGA technology. This evaluation is a gate to further consideration of an embedded FPGA soft processor implementation.

Performance and Power
Two potentially critical system factors include the desired functionality and operational performance as well as the power required to implement the desired system functionality. There will typically be a delta between the power consumption and level of performance for fixed function processor implementations and potentially more flexible FPGA-based soft processor cores.

In order to compare the relative performance of soft processor cores a common processor benchmark approach must be used. Currently the most common benchmark is the DMIPS (Dhrystone Million Instructions Per Second) benchmark. The DMIPS benchmark is based on running an algorithm on a targeted processor core to measure its integer processing capabilities within a defined time period.

Additional performance considerations include the architecture of the soft processor core and its suitability for the targeted application. Factors to evaluate include:

• Type and size of the memory and peripheral bus
• Size and model of address space
• Type and size of cache (Instruction/data)
• Type of controllers like DMA and interrupt structure
• Hardware accelerator capability (co-processor functionality)
• Functional units such as the register file and execution units
• Type of pipeline and strategies to prevent stalls such as branch prediction

Several factors influence power consumption including speed of operation, the number and type of resources required to implement the soft processor core and the characteristics of the FPGA component including static and dynamic power consumption vs. operational speed and temperature. One of the challenges associated with FPGA design is the difficulty of estimating power consumption. In an ideal development flow, schedule and resources will be allocated to design evaluation on a targeted development platform with an identical target FPGA component and soft processor implementation. Design and Development Tools
The features and ease of use of the tool suite should be considered along with the tool design flow. Effective tool evaluation and analysis is important. The following factors can have a significant effect on design cycle efficiency:

• Ease of use and feature set
• Design tool flow
• Development environment tool maturity
• Compatibility between major software releases
• Available training and quality of tool tutorials
• Debug and verification capabilities

FPGA design tools include the traditional development environments for capturing and synthesizing HDL code, simulation, place and route, debug and download of the design to the target FPGA platform (See Figure 1).

Click here for Figure 1

Operating System Considerations
Another important design factor is the ability to utilize popular operating systems (OSs). Most embedded designs on 32-bit processors include an OS to reduce the design time of the software by providing an abstraction interface level to the software. Most operating systems include the OS and any lower-level software required to connect the OS to the hardware. This collection of software elements is commonly referred to as a board support package (BSP). The BSP can include items such as the processor boot code and interrupt service routines for peripherals.

Some important OS considerations include interrupt latency, kernel size, implementation of a robust set of services, and a collection of full-featured middleware. Some example middleware components include:

• USB stack
• TCPI/IP stack
• Embedded web server
• Encryption algorithms
• Wireless Ethernet connection

Processor cores typically have a list of certified operating systems that have been pre-verified. If the design team does not have experience with the selected OS, it is advantageous for the team to be trained on the specifics of the OS to reduce development time and eliminate issues that could be encountered during development. Typical OS components include:

• Task services
• Priority levels
• Timer management
• Memory management
• Application programmers interface (API)
• Inter-task communication and synchronization

• Simulation (behavioral and timing)
• Timing analysis
• Embedded logic analyzers and embedded bus analyzers
• Software simulators
• Non-intrusive real-time software debugger
• Trace capability
• Hardware / Software logic analyzer triggers
• Board-level visual indicators, signal access ports and input control signals
• Standardized debug interface via JTAG bus

• Training: seminars, demos, and tutorials
• Access to design examples, and reference code with sufficient documentation
• Access to both local and factory technical resources as required
• Technical support specialized in soft processor design
• Evaluation and boards with a sufficient range of functionality
• Access to device and tools errata
• Design issue and answer databases
• Complete and up-to-date documentation

• Issue: Power consumption
• Action: Verify consumption on an evaluation board before final target board design and layout
• Issue: Underestimating the FPGA resources required to implement the complete soft processor solution including all peripherals and bus structures
• Action: Implement design and analyze utilization report
• Issue: Incomplete understanding of the impact of a soft processor’s bus structure, memory interface overhead and peripheral interface speed on overall performance
• Action: Verify performance and functionality by implementing a design on a target evaluation board early in the design cycle
• Issue: Not implementing or maintaining sufficient design margin for design migration and expansion
• Action: Select target FPGA components with room for growth with a common package to support potential future design enhancements

The tools required to implement a MicroBlaze processor design include a Xilinx Embedded Development Kit (EDK), Xilinx FPGA design tool (ISE) and Mentor Graphics Simulation Tool ModelSim. The primary tools within EDK include Xilinx Platform Studio (XPS) and Software Development Kit (SDK). XPS is used to build and configure the processor base system. This tool supports the implementation of the soft processor core and associated peripherals, memory map, bus interconnections, hardware and software configuration and creation of low-level drivers.

The tool flow utilizes the ISE toolset to synthesize and implement (place and route) the soft processor and associated peripherals. When building a soft processor system XPS supports a simplified design flow leveraging existing evaluation board configurations. This design flow is called base system builder. The SDK environment is an Eclipse-based implementation that supports efficient standardized software development and debug. Within the SDK environment it is possible to simulate the code targeted to the soft processor target using either a cycle-accurate simulator or a virtual hardware platform capable of providing visual feedback within a console-based window supporting emulating system I/O functionality. Design debug can be performed on the target hardware system via a JTAG bus interface. Xilinx’s ChipScope Pro software provides another level of embedded logic and bus analysis capability to support FPGA system-level design evaluation and debug.

The design example is a Xilinx MicroBlaze soft-core processor implementation optimized for performance. The target FPGA device is a Spartan-3 XCV3S1500 speed grade-5 component. The Spartan-3 family has been cost-optimized for cost-sensitive applications. The benchmarked design example includes UART and timer functions to support the required benchmark functionality. The soft processor implementation also includes a single FSL port, a single hard multiplier, pattern-compare instructions and a barrel shifter block. Processor execution is out of on-chip memory to ensure maximum processor performance. This benchmark implementation utilizes 1,318 LUTs and achieves an operational speed of 100 MHz. The benchmark performance achieved is 92 DMIPs (Dhrystone 2.1) for a relative performance level of 0.92 DMIPS/MHz.

Another potential system consideration is the implementation of an operating system for the MicroBlaze soft processor core. The Operating System options for the MicroBlaze soft processor are restricted by the absence of an MMU block. Operating systems which currently support MicroBlaze include:

This article presents the implementation of soft-core processors in FPGAs, and some of the decisions and design tradeoffs which must be made during the design process. Making informed decisions during the design process reduces the time required to design, implement, debug and test an FPGA soft processor-based project. Important design factors are reviewed, common design oversights are discussed and a benchmarked design example is presented. The design example reviews required tools, tool flow and interaction and potential operating system options.

Soft processor design teams will benefit from a system-oriented design approach, which considers the long-term effects of design decisions at each design phase. With a solid understanding of the overall design cycle, development tools options, and benefits of key design trade-studies, the design team can avoid many common design mistakes and oversights resulting in a more efficient and flexible design cycle.

About the Authors
RC Cofer has more than 19 years of embedded design experience, including real-time DSP algorithm development, high-speed hardware, ASIC and FPGA design and systems engineering. His technical focus is on rapid system development of high-speed DSP and FPGA-based designs. RC holds an MSEE from the University of Florida and a BSEE from Florida Tech. He has presented at conferences on DSP and FPGA topics and is the co-author of the book Rapid System Prototyping with FPGAs published by Elsevier.

Ben Harding has 15+ years of hardware design experience including high-speed design with DSPs, network processors, and programmable logic. He also has embedded software development experience in areas including voice and signal processing, algorithm development and board support package development for numerous Real-Time Operating Systems. Ben has a BSEE from University of Alabama-Huntsville with post-graduate studies in Digital Signal Processing, parallel processing and digital hardware design. Ben has presented on FPGA and processor design at several conferences and is the co-author of the book Rapid System Prototyping with FPGAs published by Elsevier.