English
OCP-based memory access arbitration for a digital sampling oscilloscope
By Traian Tulbure and Dan Nicula, eASIC
Programmable Lgic Designline
The current approach for designing an integrated circuit in the form of a System-on-Chip (SoC) is based on reusing the models for modules with a well-defined functionality. For easier interconnection, these intellectual property (IP) cores should have an interface that obeys the rules of a standard socket.
The Open Core Protocol (OCP) is a common standard for IP core interfaces, or sockets, which facilitates the concept of "plug and play" design for SoCs. This paper presents the use of the OCP with regard to implementing a multi-port access memory with a single port SRAM. The study case is a digital sampling oscilloscope (DSO) implemented on a FlexASIC device from eASIC. The general capabilities of the chip include a two-channel digital sampling DSO and an arbitrary waveform generator (AWG) in a single USB-powered module.
The chip is implemented on Structured eASIC fabric that includes single port SRAM blocks. The on-chip SRAM is shared between the DSO and the AWG. Furthermore, the CPU also requires access to the memory; thus, a time-multiplexed memory access subsystem was designed. The OCP protocol was chosen to provide access and arbitration of the SRAM access on a 96 bit wide data bus.
Programmable Lgic Designline
The current approach for designing an integrated circuit in the form of a System-on-Chip (SoC) is based on reusing the models for modules with a well-defined functionality. For easier interconnection, these intellectual property (IP) cores should have an interface that obeys the rules of a standard socket.
The Open Core Protocol (OCP) is a common standard for IP core interfaces, or sockets, which facilitates the concept of "plug and play" design for SoCs. This paper presents the use of the OCP with regard to implementing a multi-port access memory with a single port SRAM. The study case is a digital sampling oscilloscope (DSO) implemented on a FlexASIC device from eASIC. The general capabilities of the chip include a two-channel digital sampling DSO and an arbitrary waveform generator (AWG) in a single USB-powered module.
The chip is implemented on Structured eASIC fabric that includes single port SRAM blocks. The on-chip SRAM is shared between the DSO and the AWG. Furthermore, the CPU also requires access to the memory; thus, a time-multiplexed memory access subsystem was designed. The OCP protocol was chosen to provide access and arbitration of the SRAM access on a 96 bit wide data bus.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- OCP-based Memory Controller IP Offers Optimal Power and Performance Requirements for 3G Applications
- Video codecs in SoCs using OCP-based programmable accelerator design
- A comprehensive approach for verification of OCP-based SoCs
- A comprehensive approach for verification of OCP-based SoCs
- Achieving High Performance Non-Volatile Memory Access Through "Execute-In-Place" Feature
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)