English
Chip assembly challenges and solutions
Shankar Krishnamoorthy, Sierra Design
01/23/2006 9:00 AM EST, EE Times
At nanometer technologies, IC physical design teams are designing multi-million gate systems-on-chip (SoCs) with very complex functionality including different processor cores, memory blocks, soft and hard intellectual property (IP) blocks, and analog circuitry on a single chip. In addition to addressing the sheer size and complexity, designers also need to deal with variations in design modes, environmental conditions, manufacturing steps, and device and interconnect behavior.
In recent years, hierarchical design flows have gained traction for the implementation of multi-million gate SoCs. However, with increasing design sizes, these flows using the current generation of physical implementation tools are severely strained to meet the chip specifications with aggressive schedules. Engineers have historically used a hierarchical chip design methodology (breaking the chip into pieces or blocks) to extend the capacity of design-automation tools, improve tool runtimes, and contain last minute design changes. A hierarchical design flow typically includes:
- Chip planning (design partitioning, time budgeting, block placement, pin assignment, power and clock planning).
- Block implementation (placement, clock tree synthesis (CTS), optimization, routing).
- Chip assembly (block instantiation, top level glue logic optimization, top level CTS/routing, global wire buffering, power and clock routing).
Any wrong decisions or assumptions made during chip planning and block implementation are exposed at this stage, which typically leads to unnecessary iterations and missed market opportunities. Due to the late surprises in chip assembly, design teams have rushed to incorporate chip assembly as part of concurrent engineering with the block implementation. In this article we will review chip assembly challenges and discuss the requirements of an implementation system that comprehensively addresses all the issues.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design
- Key considerations and challenges when choosing LDOs
- Reliability challenges in 3D IC semiconductor design
- Handling the Challenges of Building HPC Systems We Need
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- An Outline of the Semiconductor Chip Design Flow
- Design Rule Checks (DRC) - A Practical View for 28nm Technology
- Synthesis Methodology & Netlist Qualification