English
TSMC GF Intel Samsung Fractional-N Frequency Synthesizer PLL
System synchronization styles and trends
Sandeep Srinivasan, Synchronous Design Automation
Eby G. Friedman, University of Rochester, New York
(03/06/2006 9:00 AM EST), EE Times
This article describes emerging trends in synchronizing digital ICs and shows how process scaling, rapid increases in clock frequencies, and demand for lower power dissipation will affect the choice of synchronization styles going forward.
System synchronization controls the flow of events in a system. In the same manner that all signals are, in reality, analog in nature, all timing is in reality asynchronous. Despite this characteristic, local timing constraints can be placed on a system to permit the system to behave as if the system is completely synchronous.
This strategy uses a central clock signal to control the relative timing of events and is called synchronous clocking. Fully synchronous clocking makes it easier to understand the temporal behavior of events in a hardware system with reference to a clock edge.
Eby G. Friedman, University of Rochester, New York
(03/06/2006 9:00 AM EST), EE Times
This article describes emerging trends in synchronizing digital ICs and shows how process scaling, rapid increases in clock frequencies, and demand for lower power dissipation will affect the choice of synchronization styles going forward.
System synchronization controls the flow of events in a system. In the same manner that all signals are, in reality, analog in nature, all timing is in reality asynchronous. Despite this characteristic, local timing constraints can be placed on a system to permit the system to behave as if the system is completely synchronous.
This strategy uses a central clock signal to control the relative timing of events and is called synchronous clocking. Fully synchronous clocking makes it easier to understand the temporal behavior of events in a hardware system with reference to a clock edge.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Emerging Trends and Challenges in Embedded System Design
- Using IEEE-1588 transparent clocks to improve system time synchronization accuracy
- Why Transceiver-Rich FPGAs Are Suitable for Vehicle Infotainment System Designs
- Arteris System IP Meets Arm Processor IP
- FPGA Market Trends with Next-Gen Technology
New Articles
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
- How the Ability to Manage Register Specifications Helps You Create More Competitive Products
- EAVS - Electra IC Advanced Verification Suite for RISC-V Cores
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)