Common programming models for use on a dual-core processor
Mar 22 2006 (12:05 PM), Embedded.com
As embedded processors become more computationally capable, many new (and more advanced) algorithms can be ported, which in turn enable new applications. The most flexible architectures scale from low-end to high-end applications, enabling a common development platform across projects as well as providing more flexibility for development teams.
One way processor vendors provide the desired scalability with a single architecture is to include both single- and dual-core platforms. The goal with a multi-core processor is to allow nearly ideal scaling without overcomplicating the programming model. For example, in a dual-core system, the goal is to achieve as close to a 2x performance increase as possible.
In this paper, we will discuss the most common programming techniques for maximizing performance, as well as some system-related topics that commonly arise when porting to a dual-core processor.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related Articles
- An Example Verification Environment for Different Types of Processor Models
- Optimize inter-processor communication in dual baseband dual mode handsets
- Choosing between dual and single core media processor configurations in embedded multimedia designs
- Using PSS and UVM Register Models to Verify SoC Integration
- The role of cache in AI processor design
New Articles
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
- How the Ability to Manage Register Specifications Helps You Create More Competitive Products
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Synthesis Methodology & Netlist Qualification
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution