English
Common programming models for use on a dual-core processor
By Rick Gentile and David Katz, Analog Devices , Embedded.com
Mar 22 2006 (12:05 PM), Embedded.com
As embedded processors become more computationally capable, many new (and more advanced) algorithms can be ported, which in turn enable new applications. The most flexible architectures scale from low-end to high-end applications, enabling a common development platform across projects as well as providing more flexibility for development teams.
One way processor vendors provide the desired scalability with a single architecture is to include both single- and dual-core platforms. The goal with a multi-core processor is to allow nearly ideal scaling without overcomplicating the programming model. For example, in a dual-core system, the goal is to achieve as close to a 2x performance increase as possible.
In this paper, we will discuss the most common programming techniques for maximizing performance, as well as some system-related topics that commonly arise when porting to a dual-core processor.
Mar 22 2006 (12:05 PM), Embedded.com
As embedded processors become more computationally capable, many new (and more advanced) algorithms can be ported, which in turn enable new applications. The most flexible architectures scale from low-end to high-end applications, enabling a common development platform across projects as well as providing more flexibility for development teams.
One way processor vendors provide the desired scalability with a single architecture is to include both single- and dual-core platforms. The goal with a multi-core processor is to allow nearly ideal scaling without overcomplicating the programming model. For example, in a dual-core system, the goal is to achieve as close to a 2x performance increase as possible.
In this paper, we will discuss the most common programming techniques for maximizing performance, as well as some system-related topics that commonly arise when porting to a dual-core processor.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- An Example Verification Environment for Different Types of Processor Models
- Optimize inter-processor communication in dual baseband dual mode handsets
- Choosing between dual and single core media processor configurations in embedded multimedia designs
- Using PSS and UVM Register Models to Verify SoC Integration
- The role of cache in AI processor design
New Articles
- How to Design Secure SoCs: Essential Security Features for Digital Designers
- System level on-chip monitoring and analytics with Tessent Embedded Analytics
- What tamper detection IP brings to SoC designs
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware
- Understanding MACsec and Its Integration