FPGA partial reconfiguration mitigates variability
(04/03/2006 9:00 AM EDT), EE Times
Design variability is rapidly becoming the “norm” for electronics products. From packaging to logic functionality, electronic end products are expected to be more customized and configurable based on customer demand and field environment.
For logic design, this means the hardware must be able to handle a variety of functions, which leads to more devices and more real estate. A common method to handle this additional functionality has been to move them into switchable software modules handled by a microprocessor. However, a growing number of applications are relying on FPGA-based partial reconfiguration technology to leave logic functions in hardware, switch them in and out on demand — all while leaving your core logic running.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related Articles
- How partial dynamic reconfiguration helped make an FSK demodulator
- Partial reconfiguration in FPGA rapid prototyping tools
- An MDE Approach For Implementing Partial Dynamic Reconfiguration In FPGAs
- Accelerate partial reconfiguration with a 100% hardware solution
- Why Transceiver-Rich FPGAs Are Suitable for Vehicle Infotainment System Designs
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow