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Using complex triggers in an FPGA-based RTL debugger
By Dennis McCarty, Synplicity
April 12, 2006 -- pldesignline.com
When a design is simulated, the level of verification is a function of how accurately the simulation vectors mimic the operating environment. Designs that are simulated with vectors that accurately reflect board conditions can detect most bugs. Modeling such conditions is not easy, however, and most vectors offer only an approximation of the actual stimulus. Thus, in most cases, simulation offers only incomplete verification.
Hardware debuggers represent the ultimate system verification tool. Unlike simulators, debuggers show designers what their logic is actually doing inside the device running in the system at full speed. When using a hardware debugger it is crucial that you, as the designer, capture the precise data needed to discover bugs and verify system behavior. Not only do you need to locate the logic transitions around a certain event, but you must also track bugs that may be rare events and ensure they are trapped for closer examination.
In order to maximize efficiency, a debugger must offer probing – and display results – at the Register Transfer (RT) level, because that is the version of the design that is most familiar to the engineer. The debugger must also be able to capture any logic event of any duration or frequency and gather data based on that event. Triggering must be powerful enough to traverse a series of events so as to arrive at the particular event that is the trigger. Finally, the debugger must be able to detect events across multiple clock domains – such as metastability – that result in transitions within a period.
The Identify RTL Debugger from Synplicity provides these capabilities and many others. The tool consists of an Instrumentor to add probes and a Debugger to set trigger values and display results. The Identify software offers designers a view of logic behavior inside an FPGA operating within the system. It also offers a highly sophisticated set of trigger mechanisms that can be used to isolate just those events that are germane to a particular problem.
The following sections focus on the complex triggering capabilities of the Identify Instrumentor and Debugger that enable you to find an event or series of events that are occurring in your design. Further sections describe techniques for using the Identify product with logic analyzers to exchange triggers and augment the capabilities of both tools in system-level debug.
April 12, 2006 -- pldesignline.com
When a design is simulated, the level of verification is a function of how accurately the simulation vectors mimic the operating environment. Designs that are simulated with vectors that accurately reflect board conditions can detect most bugs. Modeling such conditions is not easy, however, and most vectors offer only an approximation of the actual stimulus. Thus, in most cases, simulation offers only incomplete verification.
Hardware debuggers represent the ultimate system verification tool. Unlike simulators, debuggers show designers what their logic is actually doing inside the device running in the system at full speed. When using a hardware debugger it is crucial that you, as the designer, capture the precise data needed to discover bugs and verify system behavior. Not only do you need to locate the logic transitions around a certain event, but you must also track bugs that may be rare events and ensure they are trapped for closer examination.
In order to maximize efficiency, a debugger must offer probing – and display results – at the Register Transfer (RT) level, because that is the version of the design that is most familiar to the engineer. The debugger must also be able to capture any logic event of any duration or frequency and gather data based on that event. Triggering must be powerful enough to traverse a series of events so as to arrive at the particular event that is the trigger. Finally, the debugger must be able to detect events across multiple clock domains – such as metastability – that result in transitions within a period.
The Identify RTL Debugger from Synplicity provides these capabilities and many others. The tool consists of an Instrumentor to add probes and a Debugger to set trigger values and display results. The Identify software offers designers a view of logic behavior inside an FPGA operating within the system. It also offers a highly sophisticated set of trigger mechanisms that can be used to isolate just those events that are germane to a particular problem.
The following sections focus on the complex triggering capabilities of the Identify Instrumentor and Debugger that enable you to find an event or series of events that are occurring in your design. Further sections describe techniques for using the Identify product with logic analyzers to exchange triggers and augment the capabilities of both tools in system-level debug.
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