Low Power USB 2.0 PHY IP for High-Volume Consumer Applications

Gervais Fong, Product Marketing Manager, Synopsys, Inc February 2006

Built-in yield optimization supports advanced technology implementation

Overview

The USB protocol has become a pervasive standard in the world of computing and consumer electronics. While few design teams would today contemplate designing their own USB intellectual property (IP), this semiconductor IP is far from commodity silicon. Synopsys introduces a second USB 2.0 PHY IP product line (titled DesignWare® USB 2.0 nanoPHY), which has been further optimized for low power, area, manufacturing cost and system performance targeted to mobile and high volume consumer applications. This offers designers a choice of highly-differentiated USB PHY cores for 0.13-micron processes and below.

Introduction

With the proliferation of USB in mobile consumer devices, there are many key criteria that design teams look for when licensing IP, such as cost, system performance (interoperability), reliability, and power. Diligent technical evaluations have become a key part of the ‘make versus buy’ decision for all but the simplest IP cores.

The competitive dynamics of global consumer electronics markets are driving down costs and putting further pressure on the design cycle. Consequently, overall design productivity and total cost of IP ownership are also issues that must be considered. For example, while the avoidance of design re-spins is a familiar design goal within most projects, the problem of reliability, in terms of field failures, can have a profound influence on the total cost of ownership. Manufacturing yield is another factor that can have a significant effect on lifetime cost. Both of these issues are directly affected by the key specification parameters of the USB PHY. Lastly, interoperability is another requirement that is critically important to interface IP. The issue of interoperability goes beyond just satisfying the requirements for ‘logo’ certification. Interoperability is a function of the design’s specification and operating margin, which in turn can impact device yield and the economics of manufacturing production.

With increasingly demanding specifications on power, driven by the need for longer operating life in portable devices, a low power design for the IP enables the overall SoC power budget to be maintained—a critical issue for battery-powered devices such as smart phones, MP3 players, digital cameras and flash drives. Within this context of an increasingly demanding set of business and technology drivers, Synopsys has introduced a second USB 2.0 PHY IP product line that is optimized for portable and high volume applications that require low power, small area, and high yield.

Synopsys’ USB 2.0 PHY Product Line

The new DesignWare USB 2.0 nanoPHY is based on and complements Synopsys’ current market-leading USB 2.0 PHY that is certified in 180-nm, 130-nm and 90-nm CMOS digital logic processes. Chosen by leading semiconductor companies, ASSP manufacturers, and foundries, the current USB 2.0 PHY product line is in high volume production with over two dozen process port and configuration combinations. Synopsys’ extensive experience in meeting rigorous quality and yield requirements with the original PHY has been applied to the development of a complementary PHY product line optimized for mobile and high-volume consumer applications. Specifically, the Synopsys DesignWare USB 2.0 nanoPHY is built on an innovative USB architecture, which has been designed to address the key issues of low power, cost and interoperability to take advantage of the latest, state-of-the-art process technologies such as 90-nm and 65-nm.

USB 2.0 nanoPHY Optimizations for Area, Power, and Pincount

Current-generation USB 2.0 PHY IP designs are typically in the region of 1mm2 to 1.2mm2 in area. Depending on the specific foundry process, the new DesignWare USB 2.0 nanoPHY breaks this size barrier by approximately 50%. This significant area reduction has been achieved through a combination of architectural and implementation optimizations. For example, a redesigned PLL/DLL architecture has eliminated the need for complex clocking circuitry, which contributes significantly to the overall reduction in area. The PHY is floorplanned in such a way that as the digital block scales with the smaller process geometries, the overall macro area is allowed to shrink—this is not always the case with mixed-signal designs.

A holistic approach to low-power design has drastically cut the power requirements for the USB 2.0 nanoPHY core. Power has been reduced in both the digital and analog blocks of the PHY. The redesigned PLL/DLL, with optimized clocking scheme, has removed the need for a significant amount of high-frequency clocking circuitry. Active power consumption is further reduced through the use of a new transmit architecture, combined with an extensively optimized clocking scheme within the receive and transmit paths. Reducing the power demands of the PHY by up to 50% not only extends battery life but also may mean that a lowercost power supply can be used. This is an important issue in portable, battery-operated products.

Figure 1. Synopsys USB 2.0 PHY and nanoPHY Comparative Power and Area

The low-power architecture has other benefits. By reducing the supply current requirement, the overall power consumption is lowered and enables the pin count to be minimized (by half) without sacrificing any functionality. The ultra-low pin count design is a major advantage in terms of enabling the use of lower-cost packaging. Alternatively, package pins can be made available for other signals. The need for fewer pins also reduces the cost of production test, as well as considerably easing SoC integration.

Yield Optimization

With the transition from 130-nm to the latest 90-nm (and below) process geometries, yield has assumed a much higher priority. With interface protocols such as USB, chip yield is linked to the performance of key specification parameters, such as PLL jitter performance and bandgap variation, as well as being dependent on chip area. A lower chip yield, even by as little as two or three per cent, can cause manufacturing cost increases which may overwhelm any savings that are achieved with a smaller die area. With this in mind, the DesignWare USB 2.0 nanoPHY includes several features that directly enhance yield through the optimization of key USB operating parameters.

First, the system design targets a high level of quality from the IP directly ‘out of the box’. This concept is illustrated by the example eye diagrams (Figure 2), which demonstrate the superior margin that is achievable when using the DesignWare USB 2.0 PHY versus another competitive PHY.

Figure 2. Example Synopsys USB 2.0 PHY Eye-Diagram Margin

There are two key USB specification parameters which are particularly challenging to meet: the rise-fall time and crossover points in the Full-Speed and Low-Speed operating modes. The new transmit circuitry in the DesignWare USB 2.0 nanoPHY, provides superior operating margin, which enables very tight control over these key USB specifications. This new architecture reduces the variation of these specifications and ensures less sensitivity to process shifts.

The USB 2.0 specification dictates that the HS/FS/LS transmitter has a controlled source impedance of 45-ohms. Therefore, one of the important PHY design tasks is to create an accurate 45-ohm on-chip source impedance. Synopsys uses a very direct method for automatically tuning the source impedance that contributes to the overall design robustness and hence, optimized yield. This new approach to tuning utilizes a reduced amount of analog circuitry and is therefore, less sensitive to process variation, as well as offering improved accuracy.

Interoperability

Many of the measures that have been taken to improve yield are also beneficial to the interoperability of the PHY. Interoperability is a requirement at two levels—between the PHY and USB digital controllers, and with other USB products. Interoperability can be straightforward to achieve if all of the components in the system are operating under typical conditions. However, foundry processes vary from slow to fast corners, PCB designs may introduce electrical variations, and even USB cabling performance may vary considerably between manufacturers. The worst case scenario is that a PHY that worked perfectly in the lab suddenly develops interoperability issues, which show up as a field failure. Such cases can be disastrous for the success of the product and extremely costly to investigate and correct.

The key to achieving excellent interoperability, even at extreme corner case operating conditions, is to aim for excellent performance margins from the default design without any modifications. This is exactly what has been achieved with the Synopsys DesignWare USB 2.0 nanoPHY IP core.

However, to deal with real world situations, a number of parameters can be adjusted to allow for systemlevel tuning of the eye shape. For most situations the default setup will be adequate and the USB PHY will work ‘out of the box’. Providing access to the key parameters which enable the eye shape to be customized ensures that the USB PHY can be set up to accommodate extreme system conditions and special cases due to process or packaging variation, without having to modify the board layout or re-spin the GDS. The key parameters can be tuned by making metal strapping changes outside the macro, without having to interfere with the internal layout.

Synopsys has an unsurpassed track record of high-speed USB and On-The-Go (OTG) logo certification and customer success at the 180-nm, 130-nm and 90-nm process nodes. The knowledge gained from all these experiences have been embedded into the design of the USB 2.0 nanoPHY. This combined with superior operating margins will help minimize the chip designer’s verification effort required during development, as well as reducing the possibility of field failures. All of these factors contribute to a lower cost of ownership.

Requirement	nanoPHY Feature
Support latest process technologies	• 130-nm, 90-nm, 65-nm • Low-power and advanced process support • Multiple foundries
Small area	• Significantly smaller (~50%) • Scalable digital block  • Optimized clocking circuitry based on new PLL/DLL architecture
Low power	• Significantly lower (~50%) • HS transmit architecture reduces peak HS current consumption • Optimized analog block reduces power • Optimized digital clocking strategy reduces digital power consumption
Low cost of ownership	• Reduced pin count ensuring simpler integration and packaging • Smaller power supply design due to reduced power consumption • Architecture, designed for yield providing excellent operating margins
Interoperability	• Excellent operating margins • System-level tuneability • Expertise in USB certification and achieving interoperability

Table 1. Synopsys USB 2.0 nanoPHY Feature Summary

Summary

Despite USB being a ubiquitous standard, clearly not all USB PHY implementations are the same. The Synopsys DesignWare USB 2.0 nanoPHY core has been designed for the latest sub-micron, low-power process nodes to offer the lowest area, power and cost for mobile and high volume consumer applications. The DesignWare USB 2.0 nanoPHY builds on the success of Synopsys’ current USB 2.0 PHY product, which has been licensed to leading semiconductor and ASSP customers accounting for tens of millions of production units. Considerable industry expertise in USB design and certification, combined with Synopsys’ robust development methodology, ensures that the USB 2.0 nanoPHY is delivered with a consistently high level of quality. Together with extensive optimization for low power and area, this approach has resulted in a USB 2.0 PHY product line that can help design teams meet their overall goals in terms of lifetime cost, power, interoperability and development timescales – the critical success factors for complex SoC development.

For more information about Synopsys’ complete DesignWare USB IP product line: http://www.synopsys.com/products/designware/usb_solutions.html