English
Constraint-driven physical design speeds IC convergence
Wilbur Luo and Craig Thompson, Cadence Design Systems
(06/26/2006 9:00 AM EDT), EE Times
As designers move to 65nm technologies and below, the convergence of performance-driven design constraints and yield-driven manufacturing constraints intensifies the demand for new approaches for integrated circuit (IC) physical design.
At these geometries, more complex manufacturing effects dramatically impact the way engineers need to tune physical designs for optimal performance and yield. Besides addressing familiar speed and capacity concerns, advanced physical design requires an architectural approach that emphasizes quality of results, more effective convergence across a broader array of constraints, and significantly greater control by designers of the physical design process itself.
Faster routing of larger designs is not enough, and design convergence means much more than area, timing and power. Instead, designers need the ability to analyze routing more effectively, and incrementally improve both performance and yield with each physical design iteration.
As the electronics industry continues to drive toward more advanced manufacturing technologies, semiconductor companies face shrinking product lifecycles and rising demand for greater functionality. For engineers, each advance in design and manufacturing capabilities brings greater challenges in every phase of development, yet dictates a greater need to reach closure on a growing list of divergent constraints arising from each stage in the development cycle.
As engineering teams move designs from high-level and detailed logic design to floorplanning and routing in physical design, they must work collaboratively to ensure that physical design maintains tight objectives for design performance, functionality and manufacturability. Accordingly, physical design and verification needs to work smoothly in the design flow, efficiently providing detailed results needed to ensure high quality results within tightening product schedules.
Yet, as designs move to deep nanometer technologies at 65nm and below, designers find that electronic design automation (EDA) tools developed even for 90nm designs are unable to address the further challenges associated with these advanced technologies. Inevitably, the lack of precise analysis of device performance at these new geometries forces design teams to make tradeoffs and concessions to ensure manufacturability.
(06/26/2006 9:00 AM EDT), EE Times
As designers move to 65nm technologies and below, the convergence of performance-driven design constraints and yield-driven manufacturing constraints intensifies the demand for new approaches for integrated circuit (IC) physical design.
At these geometries, more complex manufacturing effects dramatically impact the way engineers need to tune physical designs for optimal performance and yield. Besides addressing familiar speed and capacity concerns, advanced physical design requires an architectural approach that emphasizes quality of results, more effective convergence across a broader array of constraints, and significantly greater control by designers of the physical design process itself.
Faster routing of larger designs is not enough, and design convergence means much more than area, timing and power. Instead, designers need the ability to analyze routing more effectively, and incrementally improve both performance and yield with each physical design iteration.
As the electronics industry continues to drive toward more advanced manufacturing technologies, semiconductor companies face shrinking product lifecycles and rising demand for greater functionality. For engineers, each advance in design and manufacturing capabilities brings greater challenges in every phase of development, yet dictates a greater need to reach closure on a growing list of divergent constraints arising from each stage in the development cycle.
As engineering teams move designs from high-level and detailed logic design to floorplanning and routing in physical design, they must work collaboratively to ensure that physical design maintains tight objectives for design performance, functionality and manufacturability. Accordingly, physical design and verification needs to work smoothly in the design flow, efficiently providing detailed results needed to ensure high quality results within tightening product schedules.
Yet, as designs move to deep nanometer technologies at 65nm and below, designers find that electronic design automation (EDA) tools developed even for 90nm designs are unable to address the further challenges associated with these advanced technologies. Inevitably, the lack of precise analysis of device performance at these new geometries forces design teams to make tradeoffs and concessions to ensure manufacturability.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Multiprocessing speeds IC physical verification
- Physical Lint -- Better RTL Quality Improves Design Convergence
- Virtual prototyping speeds mixed-signal IC design
- IC Physical Design: Portable Layout and Simulation Technigues for ADSL Analog Devices
- Reliability challenges in 3D IC semiconductor design
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)