English
Aeonic Generate Digital PLL for multi-instance, core logic clocking
Cell model creation for statistical timing analysis
Ken Tseng, Altos Design Automation and Kelvin Le, Extreme DA
(07/03/2006 9:00 AM EDT), EE Times
Statistical static timing analysis (SSTA) offers a number of advantages over traditional corner based static timing analysis. Most notably, it provides a more realistic estimation of timing relative to actual silicon performance. Armed with a better answer, designers can focus their optimization efforts on the timing paths that have the biggest impact on overall performance and yield rather than paths that may fail only at extreme corners.
Meeting timing at the worst or best-case corner can be very challenging, lengthening design schedules and negatively impacting power consumption. With a large range of potential delay values, often with a difference of as much as 50 percent or more between the slow and fast process corners, it becomes harder to meet both setup times at the worst-case corner and hold times at the best-case corner.
Even if the performance goals are met, there is often an undesired impact on other design metrics, in particular power consumption, noise immunity and leakage. For example, to meet an aggressive performance target, optimization may deploy a higher ratio of low threshold cells that are faster but leakier. With statistical analysis, a better tradeoff between timing and other design metrics such as power, noise immunity can be achieved.
SSTA provides not only a list of worst timing paths, but also the probability of those paths failing while accounting for the impact of process variation. To accurately predict variation, it needs to account for both systematic variations (one example would be due to lithography) and random variations (one example would be due to doping).
Even within the same chip there is a wide range of on-chip variation (OCV). Traditional static timing tools use guard-bands or OCV factors (often as much as +/- 15%) to safeguard against OCV, but this type of over-design is too wasteful to be effective at 65nm or below. This is because at the smaller geometries the process is more sensitive to variation and over-design has an even bigger impact on leakage power. Furthermore, many of the advantages of using a costlier process node may be eliminated if too many cells are needlessly over-sized to meet an unrealistic OCV target.
(07/03/2006 9:00 AM EDT), EE Times
Statistical static timing analysis (SSTA) offers a number of advantages over traditional corner based static timing analysis. Most notably, it provides a more realistic estimation of timing relative to actual silicon performance. Armed with a better answer, designers can focus their optimization efforts on the timing paths that have the biggest impact on overall performance and yield rather than paths that may fail only at extreme corners.
Meeting timing at the worst or best-case corner can be very challenging, lengthening design schedules and negatively impacting power consumption. With a large range of potential delay values, often with a difference of as much as 50 percent or more between the slow and fast process corners, it becomes harder to meet both setup times at the worst-case corner and hold times at the best-case corner.
Even if the performance goals are met, there is often an undesired impact on other design metrics, in particular power consumption, noise immunity and leakage. For example, to meet an aggressive performance target, optimization may deploy a higher ratio of low threshold cells that are faster but leakier. With statistical analysis, a better tradeoff between timing and other design metrics such as power, noise immunity can be achieved.
SSTA provides not only a list of worst timing paths, but also the probability of those paths failing while accounting for the impact of process variation. To accurately predict variation, it needs to account for both systematic variations (one example would be due to lithography) and random variations (one example would be due to doping).
Even within the same chip there is a wide range of on-chip variation (OCV). Traditional static timing tools use guard-bands or OCV factors (often as much as +/- 15%) to safeguard against OCV, but this type of over-design is too wasteful to be effective at 65nm or below. This is because at the smaller geometries the process is more sensitive to variation and over-design has an even bigger impact on leakage power. Furthermore, many of the advantages of using a costlier process node may be eliminated if too many cells are needlessly over-sized to meet an unrealistic OCV target.
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