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How to implement a digital oscilloscope in Structured ASIC fabric
Structured ASICs provide quicker time-to-market and lower development costs than standard ASICs, while also providing higher performance and lower unit costs than FPGAs.
By Mircea Moldovan, Dan Nicula, and Traian Tulbure, eASIC Corporation
July 12, 2006 -- pldesignline.com
As the development costs for Standard-Cell design in deep-submicron technology approach the multi-million dollar level, it is inevitable that some designers will shift to an alternative solution that can reduce development costs, even if there is some penalty in overall cost or performance.
Structured-ASICs have emerged as this alternative to standard-cell design. Bridging the gap in performance and cost between Standard Cell ASICs and high-density FPGAs, Structured ASICs maintain the best aspects of both technologies. Designers can achieve quicker time-to-market and lower development costs than standard ASICs while also achieving higher performance and lower unit costs than FPGAs.
A subset of the Structured ASIC category is the Programmable ASIC, which is a Via-customizable, rather than metal-layer customized. In Programmable ASIC arrays, all metal layers are standard/pre-fabricated, out of which four layers are used for efficient segmented routing, and only a single via-layer is customized to implement a design.
The following case study describes the implementation of a digital Oscilloscope on the eASIC Programmable ASIC fabric. This design is dubbed eScope. It includes a two-channel digital sampling oscilloscope and an arbitrary waveform generator in a single USB-powered module.
eScope was implemented on a 130nm Programmable ASIC device. The chip includes the digital logic (sample buffer memory interpolating digital trigger logic, waveform output buffer memory, data sequencers, and USB IO interface logic) and interfaces to external analog circuitry and USB transceiver logic. A single on-board 80MHz oscillator drives the on-chip PLL clock generators to create separate clock domains for each digital input and output channel as well as for the USB IO channel.
The eScope is connected to a PC through USB. A graphical user interface (GUI) on the PC is used to view and process the acquired data. The following discussions detail the eScope implementation.
By Mircea Moldovan, Dan Nicula, and Traian Tulbure, eASIC Corporation
July 12, 2006 -- pldesignline.com
As the development costs for Standard-Cell design in deep-submicron technology approach the multi-million dollar level, it is inevitable that some designers will shift to an alternative solution that can reduce development costs, even if there is some penalty in overall cost or performance.
Structured-ASICs have emerged as this alternative to standard-cell design. Bridging the gap in performance and cost between Standard Cell ASICs and high-density FPGAs, Structured ASICs maintain the best aspects of both technologies. Designers can achieve quicker time-to-market and lower development costs than standard ASICs while also achieving higher performance and lower unit costs than FPGAs.
A subset of the Structured ASIC category is the Programmable ASIC, which is a Via-customizable, rather than metal-layer customized. In Programmable ASIC arrays, all metal layers are standard/pre-fabricated, out of which four layers are used for efficient segmented routing, and only a single via-layer is customized to implement a design.
The following case study describes the implementation of a digital Oscilloscope on the eASIC Programmable ASIC fabric. This design is dubbed eScope. It includes a two-channel digital sampling oscilloscope and an arbitrary waveform generator in a single USB-powered module.
eScope was implemented on a 130nm Programmable ASIC device. The chip includes the digital logic (sample buffer memory interpolating digital trigger logic, waveform output buffer memory, data sequencers, and USB IO interface logic) and interfaces to external analog circuitry and USB transceiver logic. A single on-board 80MHz oscillator drives the on-chip PLL clock generators to create separate clock domains for each digital input and output channel as well as for the USB IO channel.
The eScope is connected to a PC through USB. A graphical user interface (GUI) on the PC is used to view and process the acquired data. The following discussions detail the eScope implementation.
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