Using a multicore RTOS for DSP applications
By Mark Ireton, Ph.D., and Michael Kardonik, Freescale Semiconductor, Inc.
Mark Ireton, Ph.D., and Michael Kardonik, Freescale Semiconductor, Inc.
Semiconductor companies continue to shrink the minimum feature size of their processors, pack an exponentially increasing number of transistors onto a single die, and increase clock speeds. As a result, the industry has reached a turning point where the power dissipation of the device has become a limiting factor for processor speed. In the race to continually improve performance, we are in the midst of an epochal transition: single-core processor architectures are no longer feasible for high-end solutions, and multicore solutions are becoming the norm. This is evidenced by the success of the duel-core x86 microprocessors from both AMD and Intel, as well as the introduction of multicore DSP solutions from Freescale, TI, and Analog Devices.
While providing a solution that enables continuing performance increases, the switch to multicore architectures creates new challenges for the application programmer, such as:
- How do you communicate between processes on different cores?
- How do you ensure that shared resources are initialized before use?
- How do you share a peripheral equally between all cores?
And most importantly:
- How do you achieve all of this without making the software development process significantly more complex than in a single-core environment?
This article describes the use of a multicore real-time operating system (RTOS) that enables programmers to develop most of their code as though they were targeting a single-core device. The concepts described are general, but the particular examples are based on the SmartDSP OS, a lightweight multicore RTOS optimized for use on Freescale DSPs based on StarCore technology.
E-mail This Article | Printer-Friendly Page |
Related Articles
- Taking a multicore DSP approach to medical ultrasound beamforming
- Using scheduled cache modeling to reduce memory latencies in multicore DSP designs
- DSP system design, part 2: Critical design choices
- Embedded DSP Software Design Using Multicore a System-on-a-Chip (SoC) Architecture: Part 2
- Embedded DSP Software Design on a Multicore SoC Architecture: Part 1
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)