English
Programming heterogeneous multiprocessors
By Steve Preissig, Texas Instruments , Courtesy of DSP DesignLine
Aug 23 2006 (22:25 PM)
You may find that your best time to market, cost, and performance will come from a heterogeneous processor architecture—that is, a processor that includes both general-purpose processor (GPP) and digital signal processor (DSP) cores. Combining two or more processors into your design allows you to draw on the strengths of both, increasing your overall efficiency. Such a design, however, introduces new challenges to the software designer. How will you partition the system for optimal loading levels between the processors? How will you perform scheduling on independent processors to ensure dependent activities are executed in order and with the lowest latency? And how can you optimize inter-processor communications so that the computational benefits of a heterogeneous design are not lost to data-transfer overhead?
In this article, we will examine how to program a heterogeneous processor architecture based on the proven method of the Remote Procedure Call (RPC). We will examine how this method addresses the concerns listed above. We also explain how the RPC introduces some pitfalls, and show how they may be avoided.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Programming heterogeneous multicore embedded SoCs
- Capitalizing on the Architectural Flexibility of FPGAs with RISC-V and a Simplified Programming Flow
- Sharing NVMe SSDs for heterogeneous architectures
- Using FPGAs in Mobile Heterogeneous Computing Architectures
- Easing Heterogeneous Cache Coherent SoC Design using Arteris' Ncore Interconnect
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)