English
Analyze DSP algorithms in FPGAs fast with z-transform
By Luc Langlois, Avnet
September 18, 2006, networksystemsdesignline.com
Crafting DSP algorithms for optimum performance in hardware often requires sophisticated design techniques, such as pipelining and overclocked control logic. Such is the case for implementations using the Xilinx Virtex-4 DSP48 slice, which attains maximum efficiency when operating at its peak clock rate of 500 MHz with internal registers enabled.
However, synchronizing calculations in a structure of overclocked pipeline registers can be daunting when using traditional time-domain analysis of waveforms to visualize dataflow. The z-transform is a viable alternative. In this article, I'll present a simple, efficient methodology for analyzing high-performance DSP algorithms using the z-transform to obtain predictable results without guesswork. My examples will demonstrate quick pencil-and-paper calculation techniques of key performance metrics (such as latency) using three different structures of finite impulse response (FIR) filters, with an emphasis on Virtex-4 DSP48-based implementations.
September 18, 2006, networksystemsdesignline.com
Crafting DSP algorithms for optimum performance in hardware often requires sophisticated design techniques, such as pipelining and overclocked control logic. Such is the case for implementations using the Xilinx Virtex-4 DSP48 slice, which attains maximum efficiency when operating at its peak clock rate of 500 MHz with internal registers enabled.
However, synchronizing calculations in a structure of overclocked pipeline registers can be daunting when using traditional time-domain analysis of waveforms to visualize dataflow. The z-transform is a viable alternative. In this article, I'll present a simple, efficient methodology for analyzing high-performance DSP algorithms using the z-transform to obtain predictable results without guesswork. My examples will demonstrate quick pencil-and-paper calculation techniques of key performance metrics (such as latency) using three different structures of finite impulse response (FIR) filters, with an emphasis on Virtex-4 DSP48-based implementations.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
New Articles
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
Most Popular
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- A Heuristic Approach to Fix Design Rule Check (DRC) Violations in ASIC Designs @7nm FinFET Technology