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Using a processor-driven test bench for functional verification of embedded SoCs
By Jim Kenney, Mentor Graphics
Oct 4 2006 (12:56 PM), Embedded.com
For designs that incorporate or interface to an embedded CPU, processor driven tests can be a valuable addition to the suite of tests used to perform functional verification. Simply stated, Processor Driven Tests, or PDTs, are test vectors driven into the design via the processor bus and can originate from several types of processor models.
For a bus functional model these tests consist of a sequence of reads and writes to various register or memory locations serviced by the processor bus. In this mode, they resemble an HDL test bench where the bus functional model relieves the user of handling the complexity and detail of the bus protocol.
With a full functional model of the processor, tests in the form of embedded code are written in C or assembly and are compiled to the target processor. These tests more accurately replicate design function where the processor comes out of reset and begins fetching instructions which result in reads and writes to registers of peripherals, IP or custom logic.
A third method is to leverage the bus functional processor model to generate constrained random bus cycles. This mode is useful to load the bus with processor cycles while the ability for other bus masters to perform their data transfers is evaluated.
In this article we discuss each of these processor driven testbench methods in detail and present their strengths and weakness. We also examine the inherent value of combining PDT with traditional HDL testbenches.
Oct 4 2006 (12:56 PM), Embedded.com
For designs that incorporate or interface to an embedded CPU, processor driven tests can be a valuable addition to the suite of tests used to perform functional verification. Simply stated, Processor Driven Tests, or PDTs, are test vectors driven into the design via the processor bus and can originate from several types of processor models.
For a bus functional model these tests consist of a sequence of reads and writes to various register or memory locations serviced by the processor bus. In this mode, they resemble an HDL test bench where the bus functional model relieves the user of handling the complexity and detail of the bus protocol.
With a full functional model of the processor, tests in the form of embedded code are written in C or assembly and are compiled to the target processor. These tests more accurately replicate design function where the processor comes out of reset and begins fetching instructions which result in reads and writes to registers of peripherals, IP or custom logic.
A third method is to leverage the bus functional processor model to generate constrained random bus cycles. This mode is useful to load the bus with processor cycles while the ability for other bus masters to perform their data transfers is evaluated.
In this article we discuss each of these processor driven testbench methods in detail and present their strengths and weakness. We also examine the inherent value of combining PDT with traditional HDL testbenches.
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