DSP optimization strategies using simulators and profilers

By Eyal Bergman, CEVA, Inc.
November 20, 2006 -- dspdesignline.com

This article reveals the pros and cons of simulators and profilers. It shows how to use these tools to optimize code and to choose the right memory layout and sizing.

DSP developers face a long and growing set of challenges. The constraints a typical DSP programmer faces can be summarized by the following:

The processor computation power, in terms of available MHz, is limited due to cost and power constraints
The amount of zero-wait state (also referred to as level 1 memory) is reduced to the minimum and is usually dictated by cost constraints. In addition, there is a severe latency penalty for accessing code and data in level 2 and 3 memories as well as in external SDRAM
The latest processors have a deep pipeline (8 stages and above), which causes a severe latency penalty in the cases of pipeline breaks (e.g., false branch predictions or interrupt latency)
The consolidation of different types of tasks such as video, audio and wireless modems on a single processor requires fast and sophisticated task switching
The integration of different types of software requires complex optimizations. For example, control code demands smaller code size while real-time DSP software is constrained by cycle counts In addition to the above technology constraints, there are numerous market considerations, such as the never for product differentiation and the ever-shrinking window of opportunity for new products that dictates a short design cycle.

When developing software under so many constraints, the development environment becomes a critical factor. An effective development tool chain can enable the designer to meet the goals for the product, while an insufficient one can lead to failure. As a result, it is important to have a comprehensive, advanced and robust tool chain. Such a tool chain should include optimizing compilers, advanced debugging and analysis tools, as well as a fully featured integrated development environment (IDE). The tool chain will be most effective if it was defined in conjunction with the definition of the processor's instruction set architecture (ISA) to make full use of the ISA's features.

In the following sections, we will describe two major elements in the CEVA tool chain environment, and how these tools are utilized to improve software and increase productivity. These tools are: