English
Achieving multicore performance in a single core SoC design using a multi-threaded virtual multiprocessor: Part 2
By Kevin D. Kissell and Pete Del Vecchio, MIPS Technologies
Nov 27 2006 (0:30 AM), Embedded.com
The key to the Virtual Processor Element (VPE) approach used in the MIPS 34K core is a set of extensions of the processor's basic instruction set architecture, rather than a specific set of hardware features to enable efficient multi-threading. In the case of the 34K core, the MT ASE is an application-specific extension of the MIPS32/MIPS64 instruction set and privileged resource architecture, meaning that it is a true architectural superset.
In the light of all this, the MIPS MT ASE strives to provide a framework both for the management of parallel threads on the same CPU and for the management of parallel threads across multiple cores, and indeed for the migration of threads from one multi-threaded processor to another.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Achieving multicore performance in a single core SoC using a multi-threaded virtual multiprocessor: Part 1
- Multi-core multi-threaded SoCs pose debugging hurdles
- Optimizing performance, power, and area in SoC designs using MIPS multi-threaded processors
- Evaluating the performance of multi-core processors - Part 2
- Virtual Prototyping Environment for Multi-core SoC Hardware and Software Development
New Articles
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- How to Design Secure SoCs: Essential Security Features for Digital Designers
- System level on-chip monitoring and analytics with Tessent Embedded Analytics
- What tamper detection IP brings to SoC designs
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware
Most Popular
- System Verilog Assertions Simplified
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Design Rule Checks (DRC) - A Practical View for 28nm Technology
- How to Design Secure SoCs: Essential Security Features for Digital Designers