Design and Real Time Hardware Implementation of a Generic Fuzzy Logic Controller for a Transport/Diffusion System

by Sukrit Shankar from Conexant Systems India Pvt. Ltd. & Jaydev Sharma from IIT Roorkee & Shamim Akhtar from JIIT, Noida & Chetana Shanta Patsa from IBM, India

Abstract :

The transport/diffusion system considering the control of tracer concentration in a tubular reactor with relevant transport delay is widely used in the area of environmental engineering. They are characterized by a combination of transport delay and diffusion. As a consequence of partial mixing, their dynamic behavior may be very difficult to model.

A fuzzy controller design methodology for the control action in the transport/diffusion is presented here. The fuzzy control of the transport diffusion system is employed so that the predictive action taken as the fuzzy controller input provides benefits over the PID-controlled delay process. The efficient design of the controller according to the desired specifications using VHDL and its implementation on FPGA introduces a novel approach for realizing a generic prototype of the controller, applicable in real time systems.

Furthermore, the design of the controller in VHDL using the state chart design methodology is comparatively new in the area of hardware description languages and helps to reduce the design time significantly.

INTRODUCTION

Tubular reactors and open channels are diffusive flow systems that are characterized by a combination of transport delay and diffusion, and are widely applicable in chemical and environmental engineering [1]. In such systems, both the process and control flow cause a nonlinear variability in the transport delay. As a consequence, the transport delay variability happens to be the major difficulty, and thus constitutes an obstacle in real-time controller implementation with conventional techniques [2].

This paper considers the generic design and real time hardware implementation of a fuzzy logic controller for a flow system (with transport and diffusion), where two streams (process and control) with differing tracer concentrations enter a long pipe after mixing at the upstream end. Two DC-powered centrifugal pumps deliver water with differing ion concentrations into the mixing point at the inlet of the tubular long pipe. Sodium Chloride (NaCl) is used as the tracer and its concentration in water is measured continuously at the outlet of the tubular pipe. The concentration of NaCl in water at the outlet is observed by measuring the conductivity of the solution, which is directly proportional to the amount of tracer present in water [2].

Our control objective is to keep the outlet concentration at prescribed value by sending the output of the designed fuzzy logic controller to the control stream, regardless of the characteristics of the process stream, which may vary in an unpredictable manner [2].

BASIC PROCESS SHEME

The controller structure for which the design is carried out is not entirely based on the classical Mamdani inferential structure [3] that uses the current error and its derivative as the antecedent.

Instead, a forecasting element is introduced here along with the current steady state error as the antecedent. This forecasting element is obtained through separate block that produces a prediction of the steady-state output concentration as a function of the process and control flows [4].

The importance of introducing the predictive element lies in the fact that the system has a relevant dead-time that requires the predictive range not to be limited. The derivative used in the classical inferential structure is useful in the systems with fast dynamics where a true prediction beyond a short limit is not required. As a result, the predictive part used in the present model adapts the control action to the different operating regions, accounting for the nonlinear nature of the process.

It is now clear that the resulting controller structure is a combination of a system based on the inferential fuzzy logic, and a predictive algebraic part.

FUZZY INFERENCE SYSTEMS

The Fuzzy inference is the process of formulating the mapping from a given input to one or more outputs using fuzzy logic. The mapping then provides a basis from which decisions can be made. Fuzzy inference systems have been successfully applied in fields such as automatic control, data classification, decision analysis, expert systems, and computer vision [5].

The process of fuzzy inference involves Membership Functions, Logical Operations, and If-Then Rules.

There are five parts of the fuzzy inference process.

• Fuzzification of the input variables.
• Application of the fuzzy operator (AND or OR) in the antecedent.
• Implication from the antecedent to the consequent.
• Aggregation of the consequents across the rules.
• Defuzzification.
  

The input is always a crisp numerical value limited to the universe of discourse of the input variable and the output is a fuzzy degree of membership in the qualifying linguistic set (always the interval between 0 and 1).

As can be made out from the aforementioned theory, the fuzzy controller considered here takes the conductivity error e(k) and predicted error ep(k) as the two antecedents that determine the degree of activation of the consequent, represented by the incremental control action Äu(k), where k is the current sample. To obtain the actual control signal all the consequents are then composed with an OR connective and defuzzified.

The membership functions for the two antecedents and one consequent are defined as usual for such systems, but their normalized support values (x-axis values) is a part of the design process according to the specifications of the system.

Three qualifiers, in the form of triangular membership functions, labeled NC (Negative Conductivity Error), ZC (Zero Conductivity Error) and PC (Positive Conductivity Error), are used for the conductivity error. Three more, labeled NP (Negative Predicted Error) ZP (Zero Predicted Error) and PP (Positive Predicted Error), are used for the predicted steady-state conductivity error.

For the incremental control action, five triangular members are selected labeled NM (Negative More), NL (Negative Less), ZE (Zero), PL (Positive Less), and PM (Positive More).

Figure 1. Diagrammatic Representation of the membership function definitions for Conductivity Error, Predicted Error and the Incremental Control Action

The fuzzy control rules can be best visualized as a 2-dimensional matrix structure where the two antecedents form input entries and the values in the matrix correspond to the output. According to the nature of the system, a control table is suggested by [1]. The design process also includes the concurrent up gradation of the control table (if required) along with the design of the normalized support values for the three variables considered in the Fuzzy Logic Controller (FLC). The entire design is carried out with the ultimate aim to meet the design specifications most accurately while minimizing the error at every step.

DESIGN OF FLC IN VHDL

VHDL-based logic synthesis is an efficient method for designing complex hardware. The existing full custom or semi-custom integrated fuzzy controllers are mostly assembled from standard cells at the gate level. The design approach presented is a high-level one. The usage of high-level modeling methodologies for modeling fuzzy controllers reduces development time significantly, making rapid design of custom fuzzy hardware possible.

Field-programmable gate array (FPGA) is used as hardware platform, because they are complex enough to be used for rapid prototyping of complex systems, and for the final implementation of a chip, if only a small number of pieces are needed. FPGAs offer more flexibility than ASICs, as when a design is not needed any more; the chip can be reprogrammed for a new hardware. Thus, the FPGA based systems are flexible and can be reprogrammed unlimited number of times.

Thus, to summarize, here we have presented a design procedure with self generated design tools so as to implement a generic set of specifications pertaining to a FLC for a transport/diffusion system as a dedicated fuzzy chip, capable of performing stand alone operations, rather then to extend some general purpose processor with fuzzy instructions. Our decision is beneficial in the sense that a dedicated chip offers the highest execution speed and the design time is short, due to the usage of synthesis and high-level design tools.

The design is sped up basically by the use of manually generated graphical user interface (GUI) as statechart. For designing the rule base and the normalized support values for the three variables, we have used a high-level modeling approach instead of encoding it directly in VHDL. Translation of a high-level model into VHDL is supported, so that VHDL-based logic synthesis can be employed.

With the help of the above choice, the design time is reduced, global design functionality is evaluated in a short time, different design choices are quickly explored, edit-compile-debug cycle is fastened and most importantly the design is represented graphically in a natural and understandable way.

FPGA IMPLEMENTATION

The final implementation of the fuzzy logic controller is done using FPGA reprogrammable chip, ADCs, LCD panel and DAC.

Figure 2. Block Diagram for FPGA Implementation

The two error inputs are given to the ADCs that convert then to the 8-bit format. The digital output is generated by the VHDL code programmed onto the FPGA that is displayed on the LCD panel. The digital 8-bit format on the LCD panel is given to DAC which converts it into the corresponding analog output to be fed to the chemical processing equipments.

FLC DEISGN ENVIRONMENT

A Matlab implementation of the fuzzy logic controller for the transport/diffusion process is developed (matlab_code.m).

• ADC0808 and DAC0830 are observed and studied for their respective conversion processes.
• A Matlab Code for the generation of the Look Up Tables for the encoded values for the normalized supports is developed (generate_lut.m).
• A Matlab Code that generates the values for the two error inputs according to the desired values obtained for the output of FLC is developed (desired_values.m).
• A VHDL Code for the FPGA implementation is developed with the membership functions and the fuzzy rules considered as per the arbitrary values, and a proposed design. (vhdl_code.vhd).
• A Matlab GUI Design Tool is developed that automatically generates the parts of the VHDL Code modifying the membership functions for the two inputs and one output and the fuzzy rule base (GUI_design_tool.m).

Thus, every time the VHDL code gets modified and the results are compared to that desired.

Desired incremental control value	Encoded value (desired)	Output on FPGA (Encoded form)	Error (Hamming distance)
0.5969 0.4051 0.9316 -0.6824 -0.3983 -0.5054 -0.5855 -0.5871 -0.5114 -0.5936 -0.5151 -0.5986 -0.6019 -0.2373 -0.1633 -0.1684 -0.1554 -0.1250 -0.0915 -0.0721 -0.0613 -0.0537 -0.0471 -0.0429 -0.0403 -0.0382 -0.0372 -0.0360 -0.0362 -0.0386 -0.0435 -0.0500 -0.0560 -0.0662 -0.0786 -0.1080 -0.1853 -0.4033 0.5971 0.2426 0.1034 0.0734 0.0896 0.1576 0.3244 0.4165 0.4215 0.4169	00100110 00011010 00111100 10101100 10011010 10100000 10100101 10100110 10100001 10100110 10100001 10100111 10100111 10001111 10001010 10001011 10001010 10001000 10000110 10000101 10000100 10000011 10000011 10000011 10000011 10000010 10000010 10000010 10000010 10000010 10000011 10000011 10000100 10000100 10000101 10000111 10001100 10011010 00100110 00010000 00000110 00000101 00000110 00001010 00010101 00011011 00011011 00011011	00100110 00011011 00111100 10101100 10011010 10100011 10100101 10100110 10100000 10100110 10100001 10100111 10100111 10001110 10001010 10001011 10001010 10001000 10000010 10000101 10000100 10000011 10000011 10000010 10000001 10000010 10000010 10000010 10000011 10000010 10000011 10000011 10000100 10000100 10000101 10000100 10001100 10011010 00100110 00010000 00000110 00000111 00000110 00001011 00010101 00011011 00011011 00011011	0 1 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 1 0 1 0 0 0 0

Table 1. Comparison of the FPGA result with the desired output value

IMPORTANT POINTS IN VHDL CODE

• The multiplication of the 8-bit membership function values with the 8-bit inputs to the FLC in order to find the degree of matching is explored for complete pipelining along with the hardware complexity involved in FPGA.
• The defuzzified output being greater than 8 bits is converted to the LSB 8 bit-stream by adding the observed average error as an offset to the generalized output.
• The VHDL Code is generated to satisfy all synthesis rules completely. Though, the membership functions get initialized, they are automatically stored in RAM for further access by Xilinx ISE Development Environment.
• Loop Unrolling Optimization is done at every looping block to avoid unnecessary delays in the circuit.
• VHDL Code is taken care of the Asynchronous FPGA Risks, and hence is provided with a synchronizer module.

It is noteworthy that the entire designing is done in VHDL with a general purpose of implementing it on FPGA for prototyping. The designing for FPGA implementation could not have been done in MATLAB right from the outset as the amount of error introduced while designing in VHDL needs to be accounted for as an average amount of error to be used as the offset in the final output. The final offset equivalent to the average error due to the bit stream operation of the model throughout, is stated in results. We arrive at this average amount of error only after implementing our improved choices of designs on FPGA. The same cannot be achieved using MATLAB for FPGA implementation.

RESULTS

The offset in the output (equivalent to average error with improved designs due to entire processing of the model in bit stream format) = "01100011"

From Table 1, it is observed that

• The total number of bits differing from the desired bits = 13
• Total number of observations = 48
• Number of bits in each bit sequence = 8
• Total number of bits = 384
  

Hence, the percentage error = 13/384 * 100 = 3.38 % (Acceptable for FPGA implementation)

Device	Specification of the Xilinx XC2S300E FPGA	Used by this design
Number of CLBs used	1536	543
Number of 4 input LUTs	6144	1865
Number of IOBs	142	23
Number of gates in design	300000	19785

Table 2. Synthesis Report of FLC

CONCLUSIONS AND FUTURE WORK

The design of the controller in VHDL using the state chart design methodology is comparatively new in the area of hardware description languages and helps to reduce the design time significantly. The manual coded generation of a GUI base serving as the state chart exploits the software development environment provided in Matlab.

The fuzzy control of the transport diffusion system is employed so that the predictive action taken as the fuzzy controller input provides benefits over the PID-controlled delay process. The efficient design of the controller according to the desired specifications using VHDL and its implementation on FPGA introduces a novel approach for realizing a prototype of the controller, applicable in real time systems. A further progress in the design of the controller can be made in terms of the more generalized design of the controller with more number of inputs and more complex membership functions, generating a state chart model for the same and implementing the entire system on FPGA using VHDL.

This shall also enable the researcher to come up with a concept of better hardware approaches for the design implementation and hence exploring the entire functionalities of the reprogrammable chip.

REFERENCES

[1] Levenspiel, O., 1972. Chemical ReactionEngineering. 2nd edition. Wiley & Sons, New York.

[2] Stefano Marsili-Libelli, Alessio Colzi. Fuzzy control of a transport/diffusion system , Control Engineering Practice 6 (1998) 707–713

[3] King, P.J., Mamdani, E.H., 1977. The application of fuzzy control systems to industrial processes. Automatica 13, 235Ð242.

[4] Seborg, D.E., Edgar, T.F., Mellichamp, D.A., 1989. Process dynamics and control, Wiley Series in Chemical Engineering. [5] Zadeh, L. A. (1975). The concept of a linguistic variable and its application to approximate reasoning, Information Sciences 8: 43–80