C based design methodology accelerates ASIC/FPGA design cycles

By John Emmitt, CebaTech
January 07, 2007 -- edadesignline.com

Introduction

Electronic Design Automation is largely about saving time in the development of electronic designs. EDA tools strive to reduce verification time, design cycle time, and time to market. EDA is constantly running to try to keep up with Moore's Law, so that ever-larger chips can be produced in less time. It's commonly understood that design cycles must continue to shrink due to market pressures, and that design verification is the biggest bottleneck in today's design cycle. Verification has become a nearly insurmountable obstacle as design size and complexity have soared. Using a traditional Register Transfer Level (RTL) design flow that relies on RTL simulation for verification is no longer a viable solution. RTL simulation takes too long and costs too much.

Designing today's devices using the standard RTL methodology is becoming increasingly difficult. RTL is at too low a level of abstraction to be used effectively for the creation of very large designs. Electronic System Level (ESL) tools attempt to address this design complexity problem. Various ESL tools and languages have been created to enable designing at a higher level of abstraction; one example is SystemC, which is both a modeling language and a simulation kernel.

There are several different types of tools that fall under the ESL umbrella. There are tools that allow system-level architectural modeling and analysis. The models are generally written at a behavioral level of abstraction, perhaps using SystemC, and commonly they are transaction level models (TLMs). They may be untimed, cycle-approximate, or cycle-accurate models, depending on the simulation performance and accuracy required. System simulation is performed with these models to do profiling and performance analysis, as well as early software development. In general, there is no automatic way to take these models to a hardware implementation. Instead, time-consuming manual coding in Verilog or VHDL RTL is still required.

Other ESL tools are used to compile high-level-language (HLL) designs and generate synthesizable RTL which is then used in the standard down-stream tool flow to realize the design in silicon. Typically, the tools in this category have severe constraints on the type and size of code they can compile and may require esoteric hardware-oriented languages.

A different approach to system-level design is one in which untimed ANSI C is the design language, verification takes place in a pure C software environment, architecture is explored and implemented in the C source, and synthesizable Verilog RTL is automatically generated. Designers have a choice of a limited number of tools when they choose this methodology. One choice is the CebaTech's C2R Compiler that provides the technology to enables a C-based design methodology that can shorten time-to-market and reduce development costs for complex chips- whether they be SoC, ASIC or FPGA based designs. In addition, by enabling software algorithms to be implemented in dedicated hardware, lower cost, and lower power chips can be produced.

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