USB2.0 OTG PHY supporting UTMI+ level 3 interface - 28HK/55LL
Planning for assertion-based verification
(01/15/2007 9:00 AM EST), EE Times
One concern that is frequently raised when planning design assertions is: "How do we know that we wrote assertions that correspond to all of the behaviors of the device?" In other words, how can it be confirmed that a complete set of checks has been achieved for the features implemented by the design block?
The answer is actually quite simple. Taking a page from software engineering, we'll use an extreme-programming concept. Put concisely, this is an edict that says:
• "No implementation will be performed until a test case exists for the planned implementation."
As implementers determine which features to implement and how to implement them, they first determine how those features will be tested. Only after implementing the test case do they begin implementation of the feature itself.
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