An Analog Verification and IP Development Environment

Stephan Weber, Cadence VCAD
85622 Munich, Germany

Abstract:

This paper describes the prototype of an environment for block and sub-system analog design supported by cell-reuse and circuit-class specific templates. It brings software tools and design knowledge together which leads to higher design effectivity and quality by smoothly enhancing the usual design style.

1 Introduction

The design of digital systems is regarded as quite a clean flow; and automation in both front-end and layout, including verification is in common use. Although there is probably a lot of room for improvement [1], the analog world lacks much more of automation [2]. Analog synthesis is difficult and even the simple parametric optimization techniques are rarely used and proposed only for specific tasks like OTA/Op-Amp [3] and PLL [4] design or ¨C since a longer time ¨C for model parameter extraction and filter design.

One major reason for this non-satisfactory situation is that there are many kinds of analog parameters to be treated in design and to be verified in testbenches, whereas in digital circuits fewer parameters count (like speed, power and chip area). Although analog block complexity and component counts are often not very large, the parameter interactions can lead in practice to a much more difficult design process. The problem becomes more severe, because many modern designs are mixed-signal designs based on expensive technologies. Due to high mask costs and market pressures the need for a fast first-time success chip design is often mandatory. Beside automation by software tools, design-reuse can lead to more effectiveness in analog chip design. This paper presents a combination of these two major techniques.

Analog design is no magic black-art. Usually there are three major parts: system design, block-level design and layout (Fig.1). The major focus of this paper is on the 2nd part, i.e. the circuit design itself.

1. Specification & Top-Down System Design
2. Block Design
3. Layout, then Bottom-Up Design

Figure 1 : Analog design flow

Following this general flow, usually some iteration are needed, e.g. some blocks may become larger than expected which may lead to some changes in the floorplan or the specification needs an update.

Analog designs are usually hierarchical, but there are often no clear interfaces, one big problem with re-use. In addition there are often interactions between circuit performance and layout (speed, crosstalk, etc.) and having a well-defined procedure for the transition, e.g. by defining checkable layout constraints, is important to avoid design problems at this transition.

Whereas in digital designs often a single standard-cell library is sufficient featuring not really much different cells mainly differ in number of inputs and drive strength. However, even for relatively simple analog standard blocks like an op-amp there are many more parameters, more topologies (according to number of stages, bandwidth requirements, supply constraints, etc.) and a similar number of extra-features (such as gain or bandwidth adoption, etc.), i.e. in analog and mixed-signal design such library (Table 1) has to be much more complex and of cause any such library will only be used if its quality is high and if it covers a wide area of applications. Our new IP library features over 300 blocks of all major types in CMOS, bipolar & BiCMOS technologies.

CMOS, bipolar, BiCMOS technologies

CMOS, ECL, CML blocks

Supporting analog sub-blocks

Biasing & Power supply

Amplifiers

Nonlinear blocks

Oscillators

RF & Communications

Filters

Sub-Systems

Others

Table 1: Overview on our analog circuit block library

A further problem with analog IP libraries is that it is very difficult to make them technology-independent. Digital cells feature only NMOS and PMOS transistors, but analog ones may need many different transistor types and many other elements (like bipolar devices or even coils and other special elements).

Also most CMOS cell topologies have no need for changes even from 2um down to 65nm technologies, i.e. the simple 4-transistor NAND has been used ¨C and is best - since many, many years, whereas the analog cells need significant adoptions mainly to deal with lower supply voltages or too fully exploit the technology power of having deep-sub-micron integration.

There are of course also problems for analog synthesis and not only for IP libraries, because the trade-offs between power, impedances, signals swings, linearity, noise, etc. within block design are complex, but for luck also generally known [2].

All these difficulties on analog automation are the reason for disappointments in the past. Also tool acceptance and prejudices by the designers are problems to be addressed. EDA tools are complex enough and it is dangerous if a new environment is very much different from the well-established existing ones.

The designers experience is an important factor making analog design successful and let them avoid too many design iterations. On the other hand, it often comes out that the circuit shows bugs in the lab although the tools where powerful enough to solve the problems before tape-out, i.e. not only design speed but even more quality is a driver for an advanced analog design flow.

2 Our Approach

Analog block design is as mentioned often quite iterative ¨C with both small and larger iteration loops - especially for high-performance or RF designs. The general flow (Fig. 2) is generally accepted and quite straight-forward, although too often designers tend to skip some parts because they feel that a certain performance is "guaranteed" by the design itself and their experience.

Create or receive a circuit specification
Make initial design by hand at nominal conditions

Draw circuit topology based on older ones & experience
Make sizing by experience and manual calculations
Create testbenches & model environment and parasitics
Check operating regions and feasibility
Check DC operation, then AC, transient & noise
Do sweeps of parameters for robustness & optimization
Check suitability for layout (e.g. area)
Check design together with neighboring blocks

Do MC and PVT corner simulations:

Optimize device matching if needed
Check circuit at PVT corners and improve sizing at worst-case conditions
Check over-all yield

Do a design review
Receive layout for parasitic back-annotation:

Resimulate circuit and readjust parameters if needed

Build subsystems from block and system from sub-blocks

Figure 2: General analog circuit design flow

Practically all custom-IC environments feature tools to cover the different tasks; some even bring a lot of them together [5]. However, as mentioned the market impact is not as large as one would expect for such tools and many problems need still to be addressed. There is no "one-fits-all" in analog design, so - based on Cadence CIC flow and the well-established Virtuoso Spec-Driven Environment VSDE/VCME - five major extensions have been made in a prototype called VCME Toolbox (Fig. 5 & Table 2).

Feature	VCME	VCME Toolbox
Behavioral modeling	X	X
Block verification	X	X
Enhanced automated testbench creation		X
IP block library		X
IP reuse support		X
Quality assurance & documentation support		X
Class-specific supporting tools		X
Advanced optimization techniques		X

Table 2: VCME and VCME Toolbox extensions

The key factor is that the software should guide the designer, by having always something that work and by bringing circuits, design styles and tools closely together. Our extensions base highly on the VSDE plug-in VCME which offers already basic verification testbench creation based on class-specific user-writable templates, but (currently) supports no advanced features like built-in checklists, IP reuse, etc. The full manual design style could be still used and even fully combined with built-in procedures for best user acceptance.

On analog IP reuse many experts say that it will never work at all. To some degree this is probably correct, because a direct reuse is often not possible. Nearly always there are changes required in some electrical parameters or technology, and using the ¡°smallest common denominator¡± leads to non-optimum designs, e.g. on area, power consumption, noise, etc. Our reference IP library gives a starting point for analog design. However, this starting point is normally a very good one. The IP blocks are partially scalable and allow the designer to compare his ideas with the state-of-the-art, because in addition to the blocks there are also advanced verification testbenches available. This solves the problem that IP blocks are often rejected because they are not well-documented.

One may argue that this approach only leads to limited design-speed improvements, but on the other hand, true synthesizing tools can be easily added.

The problem of technology dependence is not as severe as it look at first glance, because analog designs often do not use minimum feature-size components in most places e.g. due to matching or reliability reasons.

For the testbench creation there is no technology adoption problem at all and adoptions are here very easy. For high user-acceptance the testbenches should look like well-designed flexible manually created testbenches.

Figure 3: Typical Toolbox testbench

Using a modular system, easy adoption and simulator-independence is guaranteed. The VCME Toolbox testbenches are class-specific, but share sub-blocks for stimuli, supply, biasing, etc. and calculator expressions and veriloga modules.

The general analog block design flow is shown in fig. 4.

Start Analog Environment VSDE

¡ý

Start Plug-in Toolbox VCME

¡ý

Select Circuit Class

¡ý

Select DUT ¨CUse existing or take it from IP lib via search function

¡ý

Map interface pins

¡ý

Define Specifications including corners & testbench variables

¡ý

Create VSDE setup for Verification ¨C Create behavioral models & make modifications/extensions if needed

¡ý

Run testbenches in VSDE

¡ý

Tweak/optimize the design

¡ý

Document your design

¡ý

Create Silicon-calibrated models for verification

Figure 4: Toolbox VCME design flow for IP reuse

The class-templates are test-files in OpenDCM language and are usually created by some specialists and define GUI entries, variables, DUT pins and the testbenches. However, simple changes can be usually done by any designer. In addition, VSDE allows full flexibility without modifying any template, so e.g. testbench extensions which are only interesting for some special blocks are usually done this way, i.e. just as usual if following a total manual design flow.

If applied in a brute-force manner, the proposed ¡°full-featured¡± block flow (see Fig. 2) might be sometimes by far too slow, which is one reason for many frustrations with optimizers in the past. Therefore the Toolbox spec setup includes additional attributes for optimization speed-up by supporting multi-step optimizations (Fig. 6). For instance, an experienced designer would focus on some key parameters only (like offset voltage) if he checks his design on device mismatch by a normally time-consuming Monte-Carlo analysis, because other parameters like rise-time typically depend only little on mismatch. That could speed up design by avoiding the very slow combination of transient and MC simulations.

3 Experiences and Conclusions

Often several calculations are needed during analog circuit or system design. This is often done manually or using Excel or small PC tools. Therefore we put such kind of tools also into our prototype to support tasks like system-level, noise and stability calculations, bipolar or CMOS amplifier design, etc. (Fig .7).

A further issue is behavioral modeling (Fig. 8) for both system planning (top-down) and verification (bottom-up). For top-down flow, specification will play again central role, whereas for bottom-up verification the models can be enhanced by using table-based models and calibrating them on the final transistor-level circuit.

Reviewing the work on and with Toolbox over three years, the main user benefit is probably flexibility, having a jump start on his designs (like RF transceivers, bandgaps, filters or switched-mode power supplies) and having a basis for IP reuse. This is hard to quantify.

All in all, we achieved a system of bricks which is still as flexible as the manual flow and features many extensions ease things regarded as boring like quality assurance by checklists, project monitoring, documentation for reuse or reviews, etc. New cell-classes and especially new IP lib blocks are simple to create and to integrate which is important to make the environment a living tool.

4 Future Works

We presented a prototype for a flexible and highly automated analog environment. Currently parts of the prototype are hard-coded and some extensions in the VCME programming language are needed.

The new Cadence CIC6.x platform with ADE-GXL also offers enhanced optimization support. Because analog optimization is difficult (e.g. convergence difficulties) and slow (e.g. long simulation times), our ¡°always have something that works¡±-approach could highly support optimization setup and usage. The current library blocks already feature design variables for the most important parameters (like width of input transistors, capacitance of frequency compensation caps, etc.) to support optimization at least of the most important circuit parameters.

For the future, extensions on the testbench library and on back-end support are planned to move to a true specification and constraint-driven front-to-back-end flow. This will base on the new 6.x constraint management system without the need of significant extensions in Toolbox itself. However, addressing layout support directly in the Toolbox IP lib could be a big lever for effective usage of constraints, because in many cases designers feel that using constraint is simply too much work, at least for a single block.

For technology transfer of reference blocks scripts should be created - e.g. involving the Virtuoso Layout Migrate tool - which of course depend highly on the target technology.

We also believe that chip design should not only regarded as a project subtask from spec to GDS, but as a IP and knowledge creation process enabling a company to do future designs more effectively; and this should be reflected in the design flow.

Special thanks to Paul Foster for his great support and the creation of VCME, also to Eyck Jentzch for review and his Cadence VCAD IP coordination work.

References

[1] Lou Scheffer, DAC 2003 DFM Tutorial

[2] Emil Hjalmarson, Studies on Design Automation of Analog Circuits, PhD Thesis 1065, Institute of Technology Linkopings University, 2003

[3] Maria del Mar Hershenson et al, Optimal Design of a CMOS Op-Amp, IEEE Transactions on Computer-Aided Design, Vol. 20, No. 1, January 2001

[4] Implementing a Full-Custom Clock Synchronization PLL, Barcelona Application Note, 2002

[5] http://www.cadence.co.jp/products/pdf/virtuoso/Spec-Driven_Environment.pdf