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The challenges of next-gen multicore networks-on-chip systems: Part 4
By Luca Benini and Giovanni De Micheli
Feb 26 2007 (0:30 AM), Embedded.com
Raising the abstraction level for computation and communication specification seems the only way to master the complexity of mapping a large software application onto an multi-processor systems-on-chip (MPSoC). Even though the bulk of this book is on architectural and lower-level issues, high-level programming models are needed to support abstraction of hardware and software architectures.
Parallel computer architectures and parallel programming have deep roots in high-performance computing. Early programming abstractions for parallel machines go back almost 60 years.
In the last half-century, the traditional dichotomy between shared memory and message passing as programming models for multi-processor systems has consolidated. For small-to-medium scale multi-processor systems consensus was reached on cache-coherent architectures based on shared memory programming model.
In contrast, large-scale high-performance multi-processor systems have converged toward non-uniform memory access (NUMA) architectures based on message passing (MP) [5, 6]. As already discussed, several characteristics differentiate NoCs and MPSoCs from classical multiprocessing platforms, and this view must be carefully revisited.
First, the "on-chip'' nature of interconnects reduces the cost of inter-processor communication. The cost of delivering a message on an on-chip network is in fact at least one order of magnitude lower (power-and performance-wise) than that of an off-chip interconnect. NoC platforms feature a growing amount of on-chip memory and the cost of on-chip memory accesses is also smaller with respect to off-chip memories.
Second, NoCs are often deployed in resource-constrained, safety-critical systems. This implies that while performance is obviously important, other cost metrics such as power consumption and predictability must be considered and reýected in the programming model.
Unfortunately, it is not usually possible to optimize all these metrics concurrently, and one quantity must typically be traded off against the other. Third, unlike traditional MP systems, most NoC architectures integrate highly heterogeneous end-nodes. For instance, some platforms are a mix of standard processor cores and application-specific processors such as digital signal processors or micro-controllers [7, 8].
Conversely, other platforms are highly modular and reminiscent of traditional, homogeneous multi-processor architectures [9, 10], but they have a highly application-specific memory hierarchy and input output interface.
Feb 26 2007 (0:30 AM), Embedded.com
Raising the abstraction level for computation and communication specification seems the only way to master the complexity of mapping a large software application onto an multi-processor systems-on-chip (MPSoC). Even though the bulk of this book is on architectural and lower-level issues, high-level programming models are needed to support abstraction of hardware and software architectures.
Parallel computer architectures and parallel programming have deep roots in high-performance computing. Early programming abstractions for parallel machines go back almost 60 years.
In the last half-century, the traditional dichotomy between shared memory and message passing as programming models for multi-processor systems has consolidated. For small-to-medium scale multi-processor systems consensus was reached on cache-coherent architectures based on shared memory programming model.
In contrast, large-scale high-performance multi-processor systems have converged toward non-uniform memory access (NUMA) architectures based on message passing (MP) [5, 6]. As already discussed, several characteristics differentiate NoCs and MPSoCs from classical multiprocessing platforms, and this view must be carefully revisited.
First, the "on-chip'' nature of interconnects reduces the cost of inter-processor communication. The cost of delivering a message on an on-chip network is in fact at least one order of magnitude lower (power-and performance-wise) than that of an off-chip interconnect. NoC platforms feature a growing amount of on-chip memory and the cost of on-chip memory accesses is also smaller with respect to off-chip memories.
Second, NoCs are often deployed in resource-constrained, safety-critical systems. This implies that while performance is obviously important, other cost metrics such as power consumption and predictability must be considered and reýected in the programming model.
Unfortunately, it is not usually possible to optimize all these metrics concurrently, and one quantity must typically be traded off against the other. Third, unlike traditional MP systems, most NoC architectures integrate highly heterogeneous end-nodes. For instance, some platforms are a mix of standard processor cores and application-specific processors such as digital signal processors or micro-controllers [7, 8].
Conversely, other platforms are highly modular and reminiscent of traditional, homogeneous multi-processor architectures [9, 10], but they have a highly application-specific memory hierarchy and input output interface.
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