English
Expanding applications for low-cost FPGAs
By Gordon Hands, Lattice Semiconductor Corp.
April 04, 2007 -- pldesignline.com
The low-cost FPGA marketplace
Over the last several years, the popularity of low-cost Field Programmable Gate Arrays (FPGAs) has increased dramatically, to the point where low-cost FPGAs now represent approximately 25% of the overall market. However, the features these products provide (or do not provide) have limited the applications that can utilize low-cost FPGAs. The challenge for FPGA providers is to increase the feature set of these devices while continuing to deliver the attractive price points that have made these devices so popular.
This article examines the need for, and approaches to, providing enhanced low-cost FPGA capability in the areas of SERDES, DSP, high-speed source synchronous I/O, memory capacity and device configuration. The article concludes with a summary of the second generation EConomy Plus FPGAs from Lattice Semiconductor, and the approaches taken to address these five capabilities.
April 04, 2007 -- pldesignline.com
The low-cost FPGA marketplace
Over the last several years, the popularity of low-cost Field Programmable Gate Arrays (FPGAs) has increased dramatically, to the point where low-cost FPGAs now represent approximately 25% of the overall market. However, the features these products provide (or do not provide) have limited the applications that can utilize low-cost FPGAs. The challenge for FPGA providers is to increase the feature set of these devices while continuing to deliver the attractive price points that have made these devices so popular.
This article examines the need for, and approaches to, providing enhanced low-cost FPGA capability in the areas of SERDES, DSP, high-speed source synchronous I/O, memory capacity and device configuration. The article concludes with a summary of the second generation EConomy Plus FPGAs from Lattice Semiconductor, and the approaches taken to address these five capabilities.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)