By Rajendra C Turakani and Ritesh Ramesh Parekh, Ittiam Systems.
Apr 11 2007 (14:17 PM), Programmable Logic DesignLine
Abstract
High-density FPGA-based boards are widely being used for logic development and verification before taping out the actual IC. On a high-density FPGA-based board where multiple FPGAs are interconnected with hundreds of signals, checking and validating the interconnections between the FPGAs becomes a very challenging task. This article describes how challenging the problem is and also suggests a simple, effective, and generic solution to check the signal connectivity between the FPGAs. The method also helps the designer to identify and locate faults, if any, on the board which otherwise would have been a very cumbersome task. This article also proposes a method to efficiently generate the test code, most of which could be automated.
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