How to write an optimized FIR filter

By Robert Oshana, Texas Instruments

April 23, 2007, dspdesignline.com

This article shows how to write optimized FIR filter code for a DSP, using the Texas Instruments C55x architecture as an example.

Today's DSP architectures are made specifically to maximize throughput of DSP algorithms, such as a DSP filter. Some of the features of a DSP include:

On-chip memory – Internal memory allows the DSP fast access to algorithm data such as input values, coefficients and intermediate values.
Special MAC instruction – For performing a multiply and accumulate, the crux of a digital filter, in one cycle.
Separate program and data buses – Allows the DSP to fetch code without affecting the performance of the calculations.
Multiple read buses – For fetching all the data to feed the MAC instruction in one cycle.
Separate Write Buses – For writing the results of the MAC instruction. Parallel architecture – DSPs have multiple instruction units so that more than one instruction can be executed per cycle.
Pipelined architecture – DSPs execute instructions in stages so more than one instruction can be executed at a time. For example, while one instruction is doing a multiply another instruction can be fetching data with other resources on the DSP chip.
Circular buffers – To make pointer addressing easier when cycling through coefficients and maintaining past inputs.
Zero overhead looping – Special hardware to take care of counters and branching in loops.
Bit-reversed addressing – For calculating FFTs.