English
TSMC 5nm (N5) 1.2V/1.8V/2.5V GPIO Libraries, multiple metalstacks
Timing Constraints Generation Technology
By Ramesh Dewangan, Atrenta Inc.
May 17, 2007 -- edadesignline.com
The need for Constraints Generation
As design complexity has scaled upward, the need to provide accurate physical constraints like timing, area, power and port locations have become increasingly important. Of these, Timing Constraints are the most difficult to provide since they depend on many external factors like floor planning, routing and integration with other blocks. Properly created timing constraints not only reduce the total effort to achieve timing closure, but also reduce the number of iterations to achieve that goal.
A typical design project goes through 10 or more iterations due to timing constraint refinement. Poor constraints impact the chip quality in terms of area, power, and timing. Subsequently, timing closure takes longer. Worst of all, incorrect constraints could result in silicon failing timing and resulting in a re-spin. There is a critical need for an EDA solution to ensure that correct timing constraints are generated and used in the design flow. Atrenta's SpyGlass-Constraints is an example of a tool that has successfully provided a validation solution to ensure the correctness, completeness and consistency of the timing constraints through a design flow (Figure 1).
May 17, 2007 -- edadesignline.com
The need for Constraints Generation
As design complexity has scaled upward, the need to provide accurate physical constraints like timing, area, power and port locations have become increasingly important. Of these, Timing Constraints are the most difficult to provide since they depend on many external factors like floor planning, routing and integration with other blocks. Properly created timing constraints not only reduce the total effort to achieve timing closure, but also reduce the number of iterations to achieve that goal.
A typical design project goes through 10 or more iterations due to timing constraint refinement. Poor constraints impact the chip quality in terms of area, power, and timing. Subsequently, timing closure takes longer. Worst of all, incorrect constraints could result in silicon failing timing and resulting in a re-spin. There is a critical need for an EDA solution to ensure that correct timing constraints are generated and used in the design flow. Atrenta's SpyGlass-Constraints is an example of a tool that has successfully provided a validation solution to ensure the correctness, completeness and consistency of the timing constraints through a design flow (Figure 1).
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- System Verilog Assertions Simplified
- Smart Tracking of SoC Verification Progress Using Synopsys' Hierarchical Verification Plan (HVP)
- Dynamic Memory Allocation and Fragmentation in C and C++
- Synthesis Methodology & Netlist Qualification